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Hi Guys,
I am using VNC to remote the cadence at home. It works fine in the simulations. But I could not be able to get the plot after the simulation. In the CIW window, I can see the error massage is " plot data failed. Wavescan may have been killed. " I went to see the 'ade-wavescan.log' file...
Hello guys,
I designed a first order delta sigma modulator in Cadence. And it is single bit. The frequency of the input signal is about 50Hz. The sampling frequency is 10KHz. I did the FFT for the output and got the spectrogram. But it looks not right. There are several lobes before 50Hz. And...
Re: cmos inverter gain
LvW, thanks very much for your explanation and suggestions. For the DC gain , I use the DC sweep simulation in cadence. Is it right? And for the AC gain, I can use the circuit as Audioguru mentioned above and do the AC simulation or the stability simulation?
Audioguru, Thank you very much for your reply.
The plot I got here is for the DC gain. The graph from DRC is for AC gain? I guess. And the plot here I did not use enough points that's why the gain is low. Attached is the new plot I got.
Re: cmos inverter gain
Hello LvW,
I want to use Cadence to simulate the DC gain and gain bandwidth of a CMOS inverter. I saw your post here and thank you for your information. I did the simulation for DC gain in Cadence and plotted Vout vs. Vin. But I could not be able to tell the slope of...
hi guys,
I am design a delta sigma modulator now. In the part of the comparator, I don't know the effect of the hysteresys of the comparator to the modulator. Is the hesteresys good or not good for the modulator. It is a switch capacitor delta sigma modulator.
I draw a comparator in Cadence...
Thanks a lot, philcorb. In the SIMULINK, there is a sampling time setup option in unit delay block. Do you mean that I need to setup the sampling time of the unit delay block as twice the sampling frequency in the system to realize the z^(-1/2) delay?
I read some papers about the delta sigma modulator and they mentioned the half-delay technology. In the paper, they usually use the switched capacitor integrator as shown in the picture.
What I am understanding is when phi1 is on, the sampling capacitor is charged to Cs*Vi(n*T-1/2*T). And then...
Is your modulator a switch capacitor modulator? If it is, the gain of the integrator may be Cs/Ci. Cs, the sampling capacitor, Ci, the integrating capacitor.
Thanks philcorb. I am not very understanding what you are saying about the half delay here. I use the integrator structure as shown in the following picture.
What I am understanding is when phi1 is on, the sampling capacitor is charged to Cs*Vi(n*T-1/2*T). And then phi1 is off and phi2 is on...
Hello guys,
I want to build a switch capacitor half-delay integrator for one second order switch capacitor sigma-delta modulator in SIMULINK. Here, the transfer function is z^(-1/2)/(1-z^(-1)). I can use the unit delay model to realize 1/(1-z^(-1)). I know I can use the variable fractional...
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