yangyang10182
Newbie level 6
hi guys,
I am design a delta sigma modulator now. In the part of the comparator, I don't know the effect of the hysteresys of the comparator to the modulator. Is the hesteresys good or not good for the modulator. It is a switch capacitor delta sigma modulator.
I draw a comparator in Cadence and got some plots. I am not sure if the outputs make sense. I will post them here. In the plot picture, you can see the differential inputs and the outputs. The outputs' plots look like not correct. But I could not tell what's wrong with it. Could some one help me out?
Thanks in advance,
I am design a delta sigma modulator now. In the part of the comparator, I don't know the effect of the hysteresys of the comparator to the modulator. Is the hesteresys good or not good for the modulator. It is a switch capacitor delta sigma modulator.
I draw a comparator in Cadence and got some plots. I am not sure if the outputs make sense. I will post them here. In the plot picture, you can see the differential inputs and the outputs. The outputs' plots look like not correct. But I could not tell what's wrong with it. Could some one help me out?
Thanks in advance,
