gm/id methodology for latched comparator

[circuitreader]

Hi all,

I am currently working on designing a latched comparator (StrongARM latch + SR latch) using the gm/Id methodology. I have all the necessary gm/Id plots but need guidance on applying this methodology to a latched comparator. For a normal OpAmp or CS amplifier, I determine currents and use formulas to find W/L ratios. However, I am unsure how to do this when incorporating a clock signal.

Thank you.

 

[D.A.(Tony)Stewart]

What does your textbook say?

What about your library?
the web ?
GPT?

https://www.seas.ucla.edu/brweb/papers/Journals/BR_Magzine4.pdf

 

[BradtheRad]

Comparator implies Hi or Lo result. When ready to store or display signal,
arrange clock pulse to send it through 'AND' gate.

Or if it's analog, a sample-and-hold circuit stores (latches) analog volt levels. Often based around a plain capacitor.

 

[dick_freebird]

Why are you fixated on this methodology stuff?

I can't count the number of product and cell op amp designs I've turned out and not once did I ever bother with this method - it wasn't a thing when I went through school and so many elements of an amplifier are sized to other concerns like noise, matching, output drive or what-have-you that any noodling over their small signal gm is wasted anyhow. Yeah, there's three or four that this really matters to. In a linear circuit. A clocked comparator is nohow, that.

 

[D.A.(Tony)Stewart]

Why are you fixated on this methodology stuff?

I can't count the number of product and cell op amp designs I've turned out and not once did I ever bother with this method - it wasn't a thing when I went through school and so many elements of an amplifier are sized to other concerns like noise, matching, output drive or what-have-you that any noodling over their small signal gm is wasted anyhow. Yeah, there's three or four that this really matters to. In a linear circuit. A clocked comparator is nohow, that.

Razavi is the current Master teacher with relevant wisdom on FET architecture. My career was long before enhancement FETs were popular and his textbooks. But my understanding was simply to use positive feedback (with hysteresis above the expected noise level) with the clock AND function. You will see the positive feedback with two inverters in series feedback of the RS latch triggered by the so-called "strongARM" detector.

The "strongARM" name was made popular by DEC and preceded by Toshiba.

Know that current mode amplifiers have higher bandwidths in both BJT and FETs, consider the increase in speed of dynamic RAM and SRAM using strongARM current mode sensing.