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Half delay integrator?

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yangyang10182

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I read some papers about the delta sigma modulator and they mentioned the half-delay technology. In the paper, they usually use the switched capacitor integrator as shown in the picture. View attachment SC integrator.bmp

What I am understanding is when phi1 is on, the sampling capacitor is charged to Cs*Vi(n*T-1/2*T). And then phi1 is off and phi2 is on, the charge stored in the Cs is discharged to Ci. So the transfer function is Cs*Vi(n*T-1/2*T)=Ci*Vo(n*T)-Ci*Vo(n*T-T). Then H(z)=(Cs/Ci)*(z^(-1/2)/(1-z^(-1))). So it is a half delay integrator. Am I understanding it correctly?

Thanks in advance!
 

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