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Half delay in Sigma-delta modulator in SIMULINK

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Feb 1, 2010
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Hello guys,

I want to build a switch capacitor half-delay integrator for one second order switch capacitor sigma-delta modulator in SIMULINK. Here, the transfer function is z^(-1/2)/(1-z^(-1)). I can use the unit delay model to realize 1/(1-z^(-1)). I know I can use the variable fractional delay model to realize z^(-1/2). It works fine in the simulation. But once I use this integrator in a delta-sigma modulator system. It always gives me an error message. I tried many ways to fix it. The message is still there. Trouble solving algebraic loop containing 'DSM_July_2011_first/SC2/Product2' at time 0. Stopping simulation. There may be a singularity in the solution. If the model is correct, try reducing the step size (either by reducing the fixed step size or by tightening the error tolerances). I tried many ways to fix the problem. The error message is still there.

Just for experiments, I changed the delay constant to 1, letting it to be a unit delay, but the error is still there. If I use the unit delay model in simulink, there is no error message. I am confused about this.

I also think if I can use the unit delay and setup the sampling time as half of the original sampling time to realize 'z^(-1/2)'. Or is there any way that I can use to realize the half-delay transfer function?

Any suggestions and ideas are very welcome.

Thanks and have a good day,


The half delay is due to the output being delayed by half the clock rate. That is, it is valid by the falling edge of the clock if the switched-cap circuit is clocked on the rising edge. If you trigger the first switched-cap integrator on the rising edge the the second switched-cap integrator on the falling edge, and so on, then that gives the z^(1/2) delay. (This is how it is actually implemented in silicon!). I believe it is possible to do this in Matlab.

Thanks philcorb. I am not very understanding what you are saying about the half delay here. I use the integrator structure as shown in the following picture.View attachment SC integrator.bmp

What I am understanding is when phi1 is on, the sampling capacitor is charged to Cs*Vi(n*T-1/2*T). And then phi1 is off and phi2 is on, the charge stored in the Cs is discharged to Ci. So the transfer function is Cs*Vi(n*T-1/2*T)=Ci*Vo(n*T)-Ci*Vo(n*T-T). Then H(z)=(Cs/Ci)*(z^(-1/2)/(1-z^(-1))). Am I understanding it correctly? If it is right, then it still has the half delay in the first order integrator. Right?

I know it should be able to do it in Matlab/SIMULINK. But I am still stuck on the half delay block. I always got error messages which I mentioned before. I will attach my .mld file here. I just did the modification on the simulink from SDtoolbox. Maybe someone would like to have a look at this file.

Any suggestions and ideas are greatly appreciated.


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It's just a question of delay. You could clock the digital at twice the rate, with alternating clocks representing a rising edge and a falling edge. You could ignore the half cycle delays, since that is all they are; they do not effect the transfer function. If you are taking out taps at different points, you just have to get the delay right. You could set T = 2T, then all the z^-1/2 go, ie doubling the simulation frequency. It is simply representation of rising and falling edges of clocks.

All these ways remove the z^-1/2 delay. By asking the simulator to simulate z^.1/2, you are asking it delay the output by half of the sample rate. It only calculates points at the sample rate, so it can't do it. If all the delays are multiples of the simulation sample rate then they occur at calculation points and all is defined nicely.

I hope that help

Thanks a lot, philcorb. In the SIMULINK, there is a sampling time setup option in unit delay block. Do you mean that I need to setup the sampling time of the unit delay block as twice the sampling frequency in the system to realize the z^(-1/2) delay?
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Hi Yangyang10182,

You're thinking in the right way! Most digital logic works on either a rising edge or a falling edge. Since this switched-cap circuit uses both rising and falling edges, you have to find a way to do this. If you clock it at twice the frequency then each alternate clock could be considered a rising edge. The clocks inbetween could be considered a falling edge. Then a z-1 block is simulated using two z-1 blocks (or z-2 block). A z-1/2 block is simulated using a z-1 block. I hope this helps

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