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Recent content by venugopala_0202

  1. V

    Interview tips for experienced (10 yrs) Physical Design Engineer

    Hi I am a PD engineer with ~10 yrs experience working in a product based company I am looking to move to some of the new entries to semicon job market (Google/Amazon etc) Of course , with 10 yrs exp, I have acquired some skill set wrt to Timing closure, Partitioning, PnR etc and worked on...
  2. V

    Usage of horizontal and vertical metal layers

    Hello Are horizontal and vertical metal routing layers strictly used only in horizontal and vertical directions? If not, what is the point of defining them as horizontal and vertical? I have this question because I have come across instances where, in the power ring a vertical metal layer was...
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    [SOLVED] why are set_min_delay and set_max_delay considered as timing exceptions?

    Hello Why are point-to-point paths constrained by set_min_delay and set_max_delay considered as timing exceptions? Are such paths considered to be not clocked? Also, when do we use these constraints? Design examples would help.
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    [SOLVED] difference between set_max_transition and set_input_transition

    Hello Can anybody please explain the difference between set_max_transition and set_input_transition constraints?
  5. V

    [SOLVED] Why does CMOS logic give complementary output?

    Hello I have a very elementary question regarding CMOS logic. Why is the CMOS output always complemetary to the desired functionality?
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    [SOLVED] DRC fixing in Cadence Encounter

    Hello Ive been trying to do some DRC fixing in Cadence Ecounter. The basic problem I am facing is offgrid/nogrid routing errors. I tried setting the routeOngrid option true and routed the design again. But still there is no significant reduction in the number of errors. The total number of DRC...
  7. V

    [SOLVED] What is via stacking?

    Hello What exactly is via stacking?? Why is it done? Why is there a constraint on the max number of vias that can be stacked? Is via stacking advantageous or disadvantageous?
  8. V

    Difference between Via and Cut??

    Hello Can anyone please tell what is the exact difference between a cut and a via?? Is it like a cut is a generic term for connection between any two layers(poly,metal,diff) and via is a type of cut for connection only between two metal layers?
  9. V

    Difference between mapping and Comaparison(LEC)

    Can anybody please tell me what is the difference between mapping and comparison in LEC???
  10. V

    Comparison between AOCV and SSTA

    Hello Can anyone please tell me how AOCV and SSTA are related or in what way one is better than the other? Is SSTA a less pessimistic and more advanced approach to timing than AOCV?
  11. V

    Cadence ETS command to find the number of input pins for a cell

    Hello Can anyone please tell me what is the command in Cadence ETS used for finding the number of input pins in a cell
  12. V

    Delay values specified for cells in the library

    I have a very basic question related to STA. If I take a library pertaining to an operating condition(fast or slow or typical) will I get two sets of delay values (max and min) for each cell in the library? This question arose when I was reading the definition for single operating condition...
  13. V

    [SOLVED] Why are high swing analog circuits less sensitive to noise?

    I just wanted to know why analog circuits with a higher swing(amplitude) less sensitive to noise in a mixed signal environment?
  14. V

    [SOLVED] How is noise induced in analog blocks due to digital blocks?

    Hello Although I do understand that it is common knowledge to isolate analog blocks from digital blocks because of the noise sensitivity of the analog circuitry, I want to understand how is it that digital blocks induce noise in analog blocks? I would appreciate it if someone could explain the...
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    Maximum number of Multicycle paths

    Is there a limit on the number of multicycle paths that can be used in a design??
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