Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by semitao

  1. S

    How to select charge pump current?

    how to select pump all, I am doing a PLL design, I don't know how to select the charge pump current. As we know, the pump current is the important fact in bandwidth, stability. And we must meet the reasonable trade-off between the value of filter components and the current. So how to do...
  2. S

    Let's talk about PLL's parameter set.

    yep, when you design your PLL, you should first design your VCO.
  3. S

    Problem with simulating PLL in FF condition

    A problem in PLL Dave, you are right, I think I should do more analysis to find the real reason.
  4. S

    Problem with simulating PLL in FF condition

    A problem in PLL Hi, guys, I have simulated my pll again, I find the spike disappear. I think maybe this is the CAD tool problem.
  5. S

    Problem with simulating PLL in FF condition

    A problem in PLL hi, xusoso, How did you solve this problem?
  6. S

    Problem with simulating PLL in FF condition

    A problem in PLL If it is the current mismatch problem, why this phenomena is periodical? I mean, if there is current mismatch, the voltage should have some trends, always decrease or increase.
  7. S

    Problem with simulating PLL in FF condition

    A problem in PLL Hi, khouly my loop filter is 2nd orde passive filter, and my pll bandwidth is 900KHz.
  8. S

    Problem with simulating PLL in FF condition

    Hi, all. I have a problem in my pll design. When I simulate the PLL circuit in tt&ss conditions, the result is OK. But when I simulate in ff condition, the output voltage of loop filter has periodical spikes. I am confused, who can help me? thanks in advance.
  9. S

    question about PLL jitter

    Type II, Order 2 passive filter. Does the type of loop filter affect?
  10. S

    question about PLL jitter

    Why? Can u tell the relationship between small pump current and detector phase noise? thanks in advance.
  11. S

    question about PLL jitter

    How about 2uA? If I use 10uA, my capacitor is very large,and I don't want to change my bandwith.
  12. S

    question about PLL jitter

    Thanks,guys, I am puzzled with how to select the charge pump current. As we know, the higher values of charge pump current lead to lower output phase noise. But the large current is limited by how large of capacitor values can be realized in the the loop filter implementation. So, I...
  13. S

    question about PLL jitter

    Hi,all. Who can tell me how to simulate the PLL jitter? When analyze the phase noise of VCO, we can use the Pnoise in spectre. I don't know how to analyse the noise from charge pump & PFD, anyone can help me? Thanks in advance.
  14. S

    question about current reference

    Hi, I want to get a current reference which has little dependence on temperature and power suplly. Who can help me? thanks in advance.

Part and Inventory Search

Back
Top