How to select charge pump current?

[semitao]

how to select pump

all,
I am doing a PLL design, I don't know how to select the charge pump current. As we know, the pump current is the important fact in bandwidth, stability. And we must meet the reasonable trade-off between the value of filter components and the current. So how to do this trade-off, what's the resonable value for charge pump current?

 

[amarnath]

choosing a charge pump current

wn=sqrt(ip*kvco)/(2*pi*N*C1).Fit in the other parameters like divider ratio, gain of the VCO and the loop filter capacitor. Overall the pump current is chosen based on noise requiremtns ,BW,lock time etc.You can refer to the book PLL frequency synthesizers by styewart to look at how a spec for a commercial PLL is specified.


amarnath

 

[butterfish]

wn=sqrt(ip*kvco)/(2*pi*N*C1).Fit in the other parameters like divider ratio, gain of the VCO and the loop filter capacitor. Overall the pump current is chosen based on noise requiremtns ,BW,lock time etc.You can refer to the book PLL frequency synthesizers by styewart to look at how a spec for a commercial PLL is specified.

amarnath

agree. and large Ip can improve the signal/noise ratio in charge pump, but usually need the larger C (die size is money) to keep the loop stability.

 

[amarnath]

Yes i understand, thats why i said it all depends on what application the PLL is going to be put to use to. For lower end applications it may not matter as much, but it is good to understand what each parameter does before choosing a value for the same for whatever application it may be.

amarnath

 

[AdvaRes]

wn=sqrt(ip*kvco)/(2*pi*N*C1).Fit in the other parameters like divider ratio, gain of the VCO and the loop filter capacitor. Overall the pump current is chosen based on noise requiremtns ,BW,lock time etc.You can refer to the book PLL frequency synthesizers by styewart to look at how a spec for a commercial PLL is specified.

amarnath

agree. and large Ip can improve the signal/noise ratio in charge pump, but usually need the larger C (die size is money) to keep the loop stability.

What is the margin of capacitance used in the design of 65 nm ASICs ?
For CMOS and RF CMOS ?