semitao
Junior Member level 3
Hi, all.
I have a problem in my pll design. When I simulate the PLL circuit in tt&ss conditions, the result is OK. But when I simulate in ff condition, the output voltage of loop filter has periodical spikes. I am confused, who can help me?
thanks in advance.
I have a problem in my pll design. When I simulate the PLL circuit in tt&ss conditions, the result is OK. But when I simulate in ff condition, the output voltage of loop filter has periodical spikes. I am confused, who can help me?
thanks in advance.