I need help simulating this circuit

[loce]

context, I have been trying to simulate this part of the circuit but for some reason not getting the results needed. Just a quick explanation of this section, when comparator U5 outputs low U9 (Pmosfet) discharges C8 quickly, which I simulated and works fine. However, the part that is not simulating correctly is when the output of comparator U5 is high, U9 will charge C8 when there is not current betweent the drain and source which will take 10s to fully dischagre. As for U10, it charges C8 quickly when the circuit powers up, meaning all capacitors are usually discharged before power up. I am posting this because all the results I get are the opposite of what I expect which makes me extremely confused as I am confident the circuit is right, so any help is extremely appreciated
below I have attached an example of what I'm getting when simulating C8 which is supposed to charge as I set it to initially be = 0

I apologize for the long post but I cant seem to figure out the problem

 

[barry]

This is quite a confusing post. Your graphs make no sense.

1. What is “vtime”?
2. Where’s your input signal?
3. “ for U10, it charges C8 quickly when the circuit powers up, meaning all capacitors are usually discharged before power up.” This does not make sense.
4. If the output of the NOR gate is low, U9 is off and VC8 is zero (as shown)

 

[KlausST]

Hi,

I agree...
additionally:
* U10 switches a node to GND
* U9 switches the same node to +5V
if both U9 and U10 are ON at the same time it causes short circuit and some smoke (at least)..

As for U10, it charges C8 quickly when the circuit powers up,

means it pulls the node to GND at power up ....
may I ask why you connect C8 to +5V?

If you connect C8 to GND you have the expected power up behaviour ... but without the need of U10.

Generally I´d say to use a cpacitor referenced to +5V (or any other voltage than GND) has to be ssen as critical.
The problem is: GND is considered as "THE REFERENCE" with no noise, zero volt.

But any other voltage will carry noise and will drift.
As long as you know this ..... and did the design for these errors .. it is OK.
But your circuit does not care for these errors.

Example: U5. The one input is "noise wise" coupled to GND. The other input is noise wise coupled to +5V. Thus a glitch in +5V will cause a glith in the output (= malfunction). As soon as you connec a capacitor in parallel to R17 both inputs are referenced to GND and are way more robust against malfunction.

****

in a circuit you have a signal flow ... from any input ... to any output.

If you don´t get the expected output ... then just trace the signal back in direction to
the input to find where the signal is like expected and where it is not like expected. That´s a simple task with a simulation tool. Just use it.

when the output of comparator U5 is high, U9 will charge C8

No. In this case there is no current through U9.
No current --> no charge


Klaus

 

[FvM]

If you want others to debug your simulation circuit, you should post a zipped simulation file along with all models not present in standard LTspice distribution.