pll initial condition, transient simulation (Vctrl)

[mssong]

My PLL gives an initial condition of 0V at the output of the VCO (it's a differential structure) and when I start the transient simulation, Vctrl starts at 1.8V, is this a normal behavior for a PLL?

 

[KlausST]

Hi,

You can decide the initial state of the simulation.
If you see "1.8V", then this most probably is the steady point.

Read the documentation of your simulator how to set initial state.

Klaus

 

[mssong]

Hi,

You can decide the initial state of the simulation.
If you see "1.8V", then this most probably is the steady point.

Read the documentation of your simulator how to set initial state.

Klaus

So, is it correct that Vctrl's value at 0s starts at 1.8V?

I thought it was normal for the Vctrl graph to look like this.

 

[KlausST]

Hi,

I underlined the "you" for a good reason.

You have to decide whether it´s correct or not. I can not decide this for you. No one can.
If you don´t want to start at 1.8V you have to tell the simulator.
Again: Read the documentation.

Klaus

 

[dick_freebird]

PLL startup is its own specialty. A loop amp which heads for the weeds
and stays there may have to have a startup circuit overlaid. You may
see "kickers", "sweepers" or even just a "switch to center" to get the loop
into sane center-seeking range.

Now in the end you'd be wanting to verify that these "patches" do the
job every time, every corner, every in-tolerance external component at
its margins.

But for the core, seeing what happens "bare" leads to "candidate mitigations"
leads to "real thing" and then verification of it all against the universe of
uses and abuses.