Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

simulating fast opamp parasitic capacitance stability question

yefj

Advanced Member level 4
Joined
Sep 12, 2019
Messages
1,195
Helped
1
Reputation
2
Reaction score
3
Trophy points
38
Activity points
7,217
Hello, here again i have a case where the parasitic capcitance of the opamp described in the third minute create a zero that ruins stability.
how exactly this zero ruins stability?
stability by definition is 0dB 180 degree phase shift.
how exactly we get a zero that ruins?
in the other example we added R that created zero that saved stability.
But here why it the opposite?
Thanks.

1706985753803.png
 

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top