Problem with simulating PLL in FF condition

[semitao]

Hi, all.
I have a problem in my pll design. When I simulate the PLL circuit in tt&ss conditions, the result is OK. But when I simulate in ff condition, the output voltage of loop filter has periodical spikes. I am confused, who can help me?

thanks in advance.

 

[mpig09]

Re: A problem in PLL

Dear semitao :

Have you checked your PFD output signals?

mpig

 

[pfd001]

A problem in PLL

it is obvious that your pll is not stabel in ff. please check your pll loop in ff corner

 

[liuyonggen_1]

Re: A problem in PLL

i am a beginner in the PLL field. could someone tell me some useful books or papers about PLL?
thanks a lot!

Added after 3 minutes:

could someone tell me some tools to simulate the circuit of PLL?

 

[khouly]

Re: A problem in PLL

what is ur loop filter topology , and what is the BW of ur loop ?

about the PLL resources
search this fourm u will find alot

also check these lec's
https://users.ece.gatech.edu/~pallen/Academic/ECE_6440/Summer_2003/ece_6440_su2003.htm
also check

R.Best PLL book it is great start

khouly

 

[neoflash]

A problem in PLL

I do not think it's stability problem. However, you do have phase margin issue. There is so much ringing in loop dynamics.

The huge spike looks like some coupling to control line voltage? (there is no way to debug in detail)

 

[gingerjiang]

Re: A problem in PLL

i have the same problem
the spike is appear periodly, and i think my pll is stable

Added after 2 minutes:


i have the same problem
the spike is appear periodly, and i think my pll is stable

 

[khouly]

Re: A problem in PLL

check the period of this signal , is it a reference spur or a VCO spur

khouly

 

[liuyonggen_1]

Re: A problem in PLL

what is ur loop filter topology , and what is the BW of ur loop ?

about the PLL resources
search this fourm u will find alot

also check these lec's
h**p://users.ece.gatech.edu/%7Epallen/Academic/ECE_6440/Summer_2003/ece_6440_su2003.htm
also check

R.Best PLL book it is great start

khouly

thanks a lot! very great help!

 

[semitao]

A problem in PLL

Hi, khouly
my loop filter is 2nd orde passive filter, and my pll bandwidth is 900KHz.

 

[eeliuliu]

Re: A problem in PLL

hi,semitao,
there are several reasons which may cause the phenomenon.
firlst, it looks like that the prescaler or divider doesn't work very well in long period. Please check them.
second, make sure there is no interference at this frequency.
third, please the PM of PLL.
fourth, ... forthur thinking...

to find the real fact, more detal information should be given.


liuliu

 

[hackjiang]

Re: A problem in PLL

May be current mismatch in the pump happened in the ff corner.

 

[wjlzhx]

A problem in PLL

yes
it is the current mismatch in the pump
i got the same problem too!!

 

[liuyonggen_1]

Re: A problem in PLL

i am a beginner in the field of PLL, could someone tell me some sumulation tools of the design of PLL?
thanks a lot!

 

[gingerjiang]

Re: A problem in PLL

i am a beginner in the field of PLL, could someone tell me some sumulation tools of the design of PLL?
thanks a lot!

hi liuyonggen_1

you can use matlab to simulate the pll in system level
spectrerf is a good simulation tool which evaluate your pll in detailed in system level or transistor level

 

[semitao]

A problem in PLL

If it is the current mismatch problem, why this phenomena is periodical?
I mean, if there is current mismatch, the voltage should have some trends, always decrease or increase.

 

[hackjiang]

Re: A problem in PLL

If it is the current mismatch problem, why this phenomena is periodical?
I mean, if there is current mismatch, the voltage should have some trends, always decrease or increase.

The current mismatch in pump cause the phenomena "reference spur".
For details, pls ref TI'S application note.Sorry,I forget the name of that material.
Maybe some other notes will explain it more clear.

 

[xusoso]

A problem in PLL

ckeck your CAD tools,do you set it right?i had the same problem before. the corner of tt and ss is right,but ff is failed.

 

[semitao]

A problem in PLL

hi, xusoso,
How did you solve this problem?

 

[adsl]

A problem in PLL

Check the PLL if there is any portion running at 25KHz (1/40us) to trace back what causes that.