Let's talk about PLL's parameter set.

[selina_wch]

Suppose PLL's bandwidth 1Meg. Division of feedback divider is from 30 to 80. How shall I set the other parameter such as Ip, Kvco, R, C1, C2? As we know, there are many trade-off among them. How to deal with those trade-off?

 

[hackjiang]

I think Kvco shoud be fixed, because VCO is ususlly designed before the loop.
Of course, the factor of Kvco shoud be treated carefully under mand trade-offs.

 

[semitao]

yep, when you design your PLL, you should first design your VCO.

 

[selina_wch]

If the output clock frequency is in some range, then Kvco is fixed usually. While if PLL's output is a fixed frequency clock, Kvco is very flexible. At this time, how to choose Kvco?

 

[sone_2907]

Am I right when I think about PLL parameter setting procedure as follow:

1. Kvco= (fmax-fmin)/(ΔVcont). Thus, the most improtant things to set up Kvco are range of VCO operating frequency and range of Vcont.

2. Ip: In order to set up value of Ip, we should consider CP ability means circuit ability. Normally, we can not deal with Ip< 10us for normal CP topology.

3. After finalize Kvco, Ip, LBW and PM, we can calculate value of Loop Filter and check them by Matlab coding or system simulation in Cadence or something else. All of four above parameters affect to Loop Filter values. Based on project requirement, we can decide values of each component in Loop Filter.

4. As far as I understanding, the trade-off we concern for PLL design is LBW >< locking time.

 

[hanjiemy]

yes, Sone_2907 is right. But the kv usually is variable base on your structure, typical 1:3, so you can consider set Icp vs. kv in order to keep the BW constant.

 

[mpig09]

Dear selina_wch :

1. Design VCO ==>That your VCO output frequency through the divider can get right frequency for your system. Than you get KVCO
2. Choose your type of filer.
3.Decide the IP value
4.Use Matlab==>when you have KVCO ,the type of filer and IP, you can write the transfer function of the pll.
5.Analysis the transfer function and verify the stable state for divider range, then you can find R, C value.


mpig