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Recent content by red_0220

  1. R

    operation voltage problem

    Hi all, I have a latch circuit that can be divided into three level (Level1,Level2,Level3) using VDD=0.5V,I plan to change VDD to 1V on Level2 of circuit. My teacher tell me a method. The method is to add a circuit of 0.5V to 1V between Level1 and Level2, then in addition a circuit of 1V to...
  2. R

    time complexity and layout

    Hi all I have two same delay circuit ,but "time complexity" are not same. Could you tell me the "time complexity" in a circuit whether influence the quality of CHIP layout ? why? thanks
  3. R

    analysis Heat Venting points in my chip.

    Hi all, I plan to do a CHIP by Astro or SOCEncounter tool. I need consider "Heat Venting points" ,and should consider which position in the chip is the hottest. How can I use Astro or SOCEncounter tool to analysis them? Thanks.
  4. R

    how to use two 4bit multipliers to make up a 8bit multiplier

    Re: how to use two 4bit multipliers to make up a 8bit multip If I want to make up 16 bit multiplier by 4 bit multiplier. Need Sixteen 4 bit multiplier at least? thanks
  5. R

    SOC encounter Power pad problem

    Hi all, I'm using umc90 to do P&R with soc encounter tool. I only finish floorplan at present and plan to make powerplan now. A problem will happen to connect power pad (Route > Special Route …) after create power-ring (Power > Power Planning > Add Rings …) . The problem show on terminal...
  6. R

    How to get the rise energy and fall energy

    Vout __/一一一\_______/一一\__/ ...........<-rise->.<-fall-> so vdd*i(vdd) and integrate it over negative cycle of output until the point where it starts rising for fall_energy (no include posedge and negedge)?
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    design a op amp with 2Vdd or 4Vdd of output voltage

    design a op amp Hi all, I plan to design a op amp , and I have a power supply(Vdd) is 5V. How can I design a op amp with 2Vdd or 4Vdd of output voltage?
  8. R

    how to use two 4bit multipliers to make up a 8bit multiplier

    Re: how to use two 4bit multipliers to make up a 8bit multip Can you tell me how to do it? Thanks. Added after 1 minutes: Can you tell me how to do it? Thanks. Added after 2 minutes: To raja.mst Can you tell me how to do it? Thanks. Added after 5 minutes: Can you tell me how to...
  9. R

    How to get the rise energy and fall energy

    Hi all, I plan to calculate a inverter internal power. I can know the internal energy equation by primepower manual. (Internal power = rise_energy + fall_energy) How to know the rise_energy and fall_energy data? I need to create a cell library.
  10. R

    how to use two 4bit multipliers to make up a 8bit multiplier

    Hi all, Could you tell me how to use two 4bit multipliers to make up a 8bit multiplier? thanks.
  11. R

    compare the difference between DFF and latch by PT problem

    Hi all I plan to compare the difference between D-Flip-Flop and latch(Two Phase Clocking) performence in pipeline multiplier by Primetime tool. But their minimun cycle time of clock are similar. How can I prove latch(Two Phase Clocking) circuits is faster than D-Flip-Flop circuits by Primetime...
  12. R

    Library compiler setup and hold time problem

    Thanks~ I intend make a circuit of mult-Vdd, so I set up different library of Vdd to need.
  13. R

    Library compiler setup and hold time problem

    Hi all, I plan to change data of cell library , I must know what are These value mean. Please help me to confirm whether error in These Figures. This is D-Flip Flop(DFF) data of cell library : cell(QDFFLTX1) { area : 17.00; cell_footprint : "QDFF" ; ff(IQ, IQN) { next_state ...
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    Library compiler builds DFF problem

    thanks~ If I want to get value of pin(D) May I be multiplied by VDD and D signal from 0 to 1 (or 1 to 0) average of current ? ( HSPICE example: .MEAS TRAN avgval AVG I(vdd) FROM=58ns ,TO=60ns Than It multiplied by VDD. )
  15. R

    Library compiler builds DFF problem

    Hi all, I plan to change data of cell library , but something I don't understand. This is D-Flip Flop(DFF) data of cell library : cell(QDFFLTX1) { . . . pin(D) { nextstate_type : data; direction : input ; capacitance : 0.001165; internal_power() { when : "!CK"...
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