Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

time complexity and layout

Status
Not open for further replies.

red_0220

Junior Member level 1
Joined
Aug 8, 2009
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,431
Hi all

I have two same delay circuit ,but "time complexity" are not same.
Could you tell me the "time complexity" in a circuit whether influence the quality of CHIP layout ? why?

thanks
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top