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HI all,
I'm verifying GPIO contrroller with APB interface using UVM.so the clock frequency i'm using is 100MHZ but later i was asked to change the clock frequency to 75MHZ .so how to genetare a stable clock with 75MHZ frequency.
This is code what i have in my mind
bit clk;
`timescale 1ns/1ns...
Hi all,
while doing formality between PRE layout and POST layout netlist in functional mode i.e scan enable is tied to ''0'',the formal verification is passing in flatten mode.But in hierarchical mode there are many failing modules.the modules are failing because reordering of logic by...
yeah.....so you mean to say...using FORMALITY tool we only check only function logic between reference and implementation....not the test logic i.e scan logic???
hi all,
i have following questions to ask while doing formality between pre-layout and post-layout netlist:
1. do we apply any constraints ??
2. do we check LEC by enabling scan logic or or we disable scan logic.
please tell me the exact procedure to do LEC between prelayout and...
hi rca,
thanks for your reply... i totally agree with you.....but how can i check whether scan insertion is done correctly or not in POST-SCAN netlist......???
Regards,
Nawaz.
hi all,
In formality while checking the logic equivalence between PRESCAN and POSTSCAN netlist ,we genreally disable the SCAN logic in scan inserted netlist i.e POSTSCAN and check it's equivalence against PRESCAN netlist and do we also the check the equivalence of POSTSCAN with scan logic...
Hi, hayoula,
what is the formality version ur using....i had the same problem with 2010 version....but when are tried my design on 2011 version...it's not getting crashed...so try running ur design on latest version of formality.
Regards.
-Nawaz.
HI all,
while doing formality i'm facing problem in schematics as follows:
there is a flip flop(in schematics) whose inputs and outputs are
AC(asynchronous clear )
SL(synchronous load)
SD(synchronous data)
CLK(clock)
Q(D...
Hi all,
what are cut points and cut nets in formality,why does a tools inserts cut points(not user defined) in netlist i,e implementation design.does this cut points will cause a verification failure ,if so what setup modification is to be done to pass the verification.
Thanks in...
Hi all,
In formality while debugging using schematics, i'm getting mismatches at input of flip flops(for example 1 at input of implementation flop and 0 at the input of reference flop).But the output is same for both the flops.so what setup modifications should be done in order to pass...
hi all,
while doing formality on scan inserted netlist against RTL ,apart from applying 0 on test_se port what are other constraints should i need to apply,in order to pass the verification.please reply ASAP.
Thanks in Advance.
Regards,
-Nawaz.
Hi all,
i'm currently working on synopsys formality.the formality tools by default checks for design CONSISTENCY...in this mode my design is getting passed but when i'm checking for design EQUALITY i'm getting failing points.is checking a design for design CONSISTENCY enough or should i...
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