mismatches at filop flop inputs during formality.

[nawaz.mjcet]

Hi all,
In formality while debugging using schematics, i'm getting mismatches at input of flip flops(for example 1 at input of implementation flop and 0 at the input of reference flop).But the output is same for both the flops.so what setup modifications should be done in order to pass the verification.

Thanks in advance.

Regards,
-Nawaz.

 

[tariq786]

can you trace the inputs to see where the two inputs are coming from? Do backtracking