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Recent content by AllenD

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    IC wirebonding question

    Hi I recently got my TSMC 65 nm IC back. I am trying to wirebonding it to my PCB. Can I please ask a few rookie questions? 1. I have a ring-like edge surrounding my IC core. I assume it is the guard ring layer I added in the end before my tapeout due date... Is that edge conductive? Meaning If...
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    IC I/O pad layout and choice

    Hi! Thanks for your reply! May I please ask a follow up question. I incline to use a Dual rank pads (aka "staggered") WITHOUT the TSMC default I/O (ESD device), though I may add a pair of diodes for personal ESD protection. But from the I/O and PAD appnote, they pair up the wire-bonding pad...
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    IC I/O pad layout and choice

    Hi Team Sorry for the long post. I am using TSMC 65nm for an IC layout. I have finished the core and I am working on the input output pads. This tape out is for my research and not for mass production. I had one tape out before. In that tapeout, I used 2 layer of pads (for more testing point and...
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    DC blocking cap and post cap DC bias design and layout

    Hi Team I am trying to design a DC blocking cap to only couple my AC signal from the first stage to the second stage of my amplifier. Can I ask a few questions? I am thinking using the most simple RC topology with a diode connected NMOS to supply the DC voltage, as in the picture. Assuming...
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    PEX with no r/c

    Hi Team May I please ask a question regarding PEX extraction. In PEX, if I select extraction type: transistor level, No R/C, No inductance, format: calibre view Use names from: schematic After the extraction, I have verified that in calibre view, the only components are mosfets (each...
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    Latch comparator decision

    Hi All I have a rookie question. This is a comparator (Song 1990) from an analog ckt design book I am reading. The basic concept of operation is: the preamp stage gives it an increased resolution and prevents kickback., track and hold latch is to boost the comparison result to digital 1 or 0...
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    [moved] D-flipflop freq divider initial phase

    Yes you are right. I delayed the reset by 0.2 clk period and both red and green case synchronized..... I guess I need to find a way to, as you suggested, Synchronous to the clock. Can you please recommend any circuit to achieve it? Just the name or keywords would be immensely helpful.
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    [moved] D-flipflop freq divider initial phase

    Thanks for your reply. I plan to add a switch off-chip to manually reset the IC. So I pick the reset signal phase randomly. Can you please elaborate on "synchronous "? synchronous to whom? If you mean for the case of red and greed, the blue reset signal is identical for both red and green cases...
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    [moved] D-flipflop freq divider initial phase

    Hi All, I am using a Hybrid Latch Flip-Flop (HLFF) circuit work as a D-flipflop, and feedback from Q_b to D to realize a freq divide by 2 circuit. My question is how to regulate the initial phase? In the attached pic on the left is the HLFF with reset and feedback. On the right: 1. Blue is the...
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    inverter Vhigh reduced

    Hi dick_freebird You are right! I found it as you said. I put 50 Ohms as the output load and the amplitude is as you predicted. I have one more question. When I use 1M Ohms for the oscilloscope input during measurement, the clock signal looks oscillating. I think it is due to signal reflection...
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    inverter Vhigh reduced

    inverter output Vhigh voltage Hi Team, I have designed a circuit with a 1.2V dc power supply. Part of the circuit is a clock generator and I output a few clock signals out to test. In order to drive more load, I adopted 4 series-connected inverter buffers before the output pad. Simulation...
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    TSMC LVS errors after sealring

    Hi I am using TSMC 65nm PDK for tape out. The LVS was clean before I add the sealring. However, when I added the sealring, the LVS complaint about 2 things: (A) Stamping conflict. Net VSS is selected for stamping. (B) the additional nets and instance. The additional device from the sealring...
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    Last step of tapeoout---sealring and dummy fill density

    Hi everyone, Can I ask a few questions concerning the last few steps of the tapeout. I am using TSMC 65nm PDK. 1. My LVS is all set without sealring. However, it reports errors when I added the sealring...It seems LVS recognize the sealring as some device. Is this my problem when I modify the...
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    TSMC I/O: pad-ESD-core connection

    Hi Team, I am using TSMC 65nm for analog circuit tapeout and I have a small question about connecting the core to the I/Os. I am using TSMC designed ESD devices, which is under the bondpad. As is known, "analog signal ESDs" is just a wire with some clamps to power supply and ground. (in other...
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    Substrate contact vialation

    Update： I verified that when I place a DCUP cell (DC decoupling cell made of mos capacitor provided by TSMC) on my layout view, the mos capacitor is automatically connected from "VDD" to "VSS", But for the analog I/O, the pin to the core circuity is called "VDD" and "AVSS". This is discrepancy...
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