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IC I/O pad layout and choice

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AllenD

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Hi Team
Sorry for the long post.
I am using TSMC 65nm for an IC layout. I have finished the core and I am working on the input output pads. This tape out is for my research and not for mass production.
I had one tape out before. In that tapeout, I used 2 layer of pads (for more testing point and break out subcircuits) and using the ESD device provided by TSMC directly placed under the 2 layer of pads. Please see in the pictures.
Screenshot from 2021-10-06 12-25-57.png
Screenshot from 2021-10-06 12-27-50.png


The question are
1. I have heard some recommendation that I can just have the pads without the ESD bacause this tape out is just for research and to prove a new concept. I don't really care about the static charge protection that much, as long as one of the chips show me great performance, then the new idea is proven. Plus the ESD device would hurt the chip performance. In my design, the signal frequency is around 2.5GHz. Is there any broad estimation how bad would the ESD device hurt the chip performance?
2. If you agree I don't need the ESD under the pads, can I still use the 2 layer pads as in the above picture? Is there any draw backs with this type of pads layout? (not all pads need to be wirebonded at the same time. Some pads are for break out circuits only)
3. If I can get rid of ESD and using the 2 layer pads, what should I put under the pads in my layout? Should I leave them empty? Should manually add fillers? Or should I connect the fillers under the pad to ground? Should I connect these fillers with the fillerd (GND VDD mesh filers) in the core of my IC?

Thanks
Al
 

AMS012

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I strongly urge you to put the ESD structure (at least the weakest ESD is also fine). It is called PDB1A cell if I remember correctly. Please do not go without ESD structure. We have seen static discharge failure for tapeouts without ESD structures in our research. Could not test a single chip in the tapeout. Make necessary design changes to accommodate a minimum ESD structure at least. Otherwise it could turn out very costly. Please do not go without ESD. At least use a pair of custom diodes.
 

dick_freebird

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It is common-enough practice for RFICs to poorly (or not at all)
protect the high frequency RF inputs. This affects things like
in-application linearity (diode C-V is a source of harmonic distortion).
In such cases you'd spec a way lower HBM ESD for a specific pin
and do your best to locate it away from high-handling-threat
(corner) pin positions. You could use very small area diodes
as a compromise, and you could try to connect them such
that the connections could be laser-cut if you want to evaluate
impact. Or place an alternate no-ESD version for direct comparo
(and handle it extra carefully).

Dual rank pads aren't much of a problem unless you are
anticipating Hi-Rel assembly and bond wire clearance visual
inspections. You might invoke special bonding instructions
like "bond die to post" to get maximum loop height at the
pads, to ensure clearance.
 

AllenD

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It is common-enough practice for RFICs to poorly (or not at all)
protect the high frequency RF inputs. This affects things like
in-application linearity (diode C-V is a source of harmonic distortion).
In such cases you'd spec a way lower HBM ESD for a specific pin
and do your best to locate it away from high-handling-threat
(corner) pin positions. You could use very small area diodes
as a compromise, and you could try to connect them such
that the connections could be laser-cut if you want to evaluate
impact. Or place an alternate no-ESD version for direct comparo
(and handle it extra carefully).

Dual rank pads aren't much of a problem unless you are
anticipating Hi-Rel assembly and bond wire clearance visual
inspections. You might invoke special bonding instructions
like "bond die to post" to get maximum loop height at the
pads, to ensure clearance.
Hi! Thanks for your reply!
May I please ask a follow up question.
I incline to use a Dual rank pads (aka "staggered") WITHOUT the TSMC default I/O (ESD device), though I may add a pair of diodes for personal ESD protection.

But from the I/O and PAD appnote, they pair up the wire-bonding pad library with different I/O library. as I highlighted in the attached picture. May I ask if I can use these pads without the ESD IO devices?
Thanks
AL
Screenshot from 2021-10-07 00-00-35.png
 

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