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inverter Vhigh reduced

AllenD

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inverter output Vhigh voltage

Hi Team,
I have designed a circuit with a 1.2V dc power supply. Part of the circuit is a clock generator and I output a few clock signals out to test. In order to drive more load, I adopted 4 series-connected inverter buffers before the output pad. Simulation suggested it can deliver 0-1.2V square waves.

When I have my IC back, I glued a piece to a PCB and wire-bonded to the 50 Ohms SMA to 50 Ohms oscilloscope. The phase relationship of the output is correct but the amplitude is wrong. The output inverter buffer is supposed biased at 0-1.2V but the oscilloscope measurement suggested the output is 0-0.9V. Moreover, when I decrease the power supply voltage (Vdd) from 1.2 to 0.9V, the output voltage high also decreases from 0-~0.6V

I have multiple ground and Vdd planes on my IC and PCB and the IR drop should not be this big in my opinion...

Does anyone have any insight into what is going on?

Thanks
 

Easy peasy

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Re: inverter output Vhigh voltage

Wow - so much helpful supporting information - ckt diagram, part numbers, type of chips used ...

don't forget only if an output line is low ohms say 1 ohm - will a 50 ohm load not drop it too much, for 50 ohm source feeding a 50 ohm load - the volts will be divided by 2 ...
 

betwixt

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Re: inverter output Vhigh voltage

In order to drive more load, I adopted 4 series-connected inverter buffers before the output pad.
How do series connected buffers increase the output capability?

Brian.
 

FvM

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You are apparently underestimating the output voltage drop with 50 ohm load. Did you include the 50 ohm load in your simulation?

Usually a 50 ohm driver has multiple parallel connected output transistors respectively multiplied W.
 

dick_freebird

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Probably an ASIC test chip.

50 ohms is definitely going to challenge even a high
drive logic buffer. If you had (say) a "10mA" buffer for
1.2V rated at 90% Vdd that says 120mV/10mA=12ohms
and so your output voltage would be Vdd*(50/(50+12))
or

(drum roll)

0.97V.

Use your own numbers and you might get closer. Run
a simulation with more realism, ditto.
 

AllenD

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Hi dick_freebird
You are right! I found it as you said. I put 50 Ohms as the output load and the amplitude is as you predicted.
I have one more question. When I use 1M Ohms for the oscilloscope input during measurement, the clock signal looks oscillating. I think it is due to signal reflection and mismatch. However, when I simulate the circuit with 1M Ohms loading, the output signal is not oscillating... Do you have any insights about it? Thanks!

- - - Updated - - -

You are apparently underestimating the output voltage drop with 50 ohm load. Did you include the 50 ohm load in your simulation?

Usually a 50 ohm driver has multiple parallel connected output transistors respectively multiplied W.
Hi FvM
You are right! I found it as you said. I put 50 Ohms as the output load and the amplitude is as you predicted.
I have one more question. When I use 1M Ohms for the oscilloscope input during measurement, the clock signal looks oscillating. I think it is due to signal reflection and mismatch. However, when I simulate the circuit with 1M Ohms loading, the output signal is not oscillating... Do you have any insights about it? Thanks!
 

FvM

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When I use 1M Ohms for the oscilloscope input during measurement, the clock signal looks oscillating. I think it is due to signal reflection and mismatch. However, when I simulate the circuit with 1M Ohms loading, the output signal is not oscillating...
You are apparently simulating without realistic cable (e.g. 50 ohms transmission line).

For medium speed source side impedance matching is a suitable solution. Connect 50 ohm series resistor between pin and coaxial cable (or 50 ohm minus driver output impedance) , connect to 1 Mohm oscilloscope input.

For high speed use source and load side matching. If the pin can't drive 100 ohm effective load, use a voltage divider, e.g. 450 ohm series resistor at source side, 50 ohm cable, 50 ohm oscilloscope input.
 

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