IC wirebonding question

[AllenD]

Hi
I recently got my TSMC 65 nm IC back. I am trying to wirebonding it to my PCB. Can I please ask a few rookie questions?

1. I have a ring-like edge surrounding my IC core. I assume it is the guard ring layer I added in the end before my tapeout due date... Is that edge conductive? Meaning If the wirebonding wires are in contact with the edge, would they short together?

2. Are the IO pad protected by a layer of insulator, which would be destroyed by wirebonding wedge? In other words, if I just land a gold wire on top of an IO pad without wirebonding wedge to smash it on the pad, is it still connected? Or the wirebonding wedge is needed to smash the gold wire to create connection to conduct current?

Thanks

 

[jjx]

1) The scribe would most likely have passivation on top, but recommendation would be to not touch it anyway...

2) If done correctly, there is an opening in the passivation above the pad surface, but due to oxidization and others you might need to stress it a bit to make the bond wire hit properly and conduct well.

 

[dick_freebird]

Pads should be cleared but storing in air will form an aluminum oxide film.
Wedge or ball bond should break through that although gross oxidation
may result in poor / inconsistent bond adhesion.

Seal ring is a series of oxide cuts which should reach the silicon surface,
in the scribe lane. Otherwise the scribe and break might peel / chip off
layers of insulation. That's a rejectable inspection criterion (if anyone
looks).

You do not want bond wires to touch anything but the bond
pads & posts. There should be a "loop" step after the wedge / ball
"coining" that imparts a vertical rise from the pad before the X-Y.
A note to assembly house saying "bond die to post" will maximize
loop height, useful for cases such as you see here that have nested
ranks of pads, and the "inners" need to clear the "outers" to prevent
shorting.