ASIC Design Methodologies and Tools (Digital)

Post thread
ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions
O
  • Question
DRC errors
Replies
4
Views
278
ThisIsNotSam
T
A
  • Question
About process corner lot
Replies
0
Views
120
asicgiga
A
C
  • Question
TARMAC Time scale trace conversion
Replies
0
Views
137
coshy
C
C
  • Question
Nwell floating when doing ERC check
Replies
2
Views
246
Chenxin Jiang
C
S
  • Question
How to load time lib data in cts of innovus
Replies
6
Views
316
Starset
S
J
  • Question
MemoryCompiler‘s SRAM LVS mismatch?
Replies
1
Views
163
ThisIsNotSam
T
C
  • Locked
  • Question
[SOLVED] Power stripe violation near the macro boundary
Replies
3
Views
346
ThisIsNotSam
T
P
  • Question
offset value measurement of sense amplifier in cadence spectre
Replies
4
Views
332
Dominik Przyborowski
J
  • Question
question on power analysis, after synthesize the verilog RTL model
Replies
3
Views
321
ThisIsNotSam
T
R
  • Question
DRC and VLS for circuit using Sky130 PDK
Replies
4
Views
897
rtl1
R
S
  • Question
innovus power IO cannot connect with power ring
Replies
11
Views
524
Starset
S
N
  • Question
Adding another pair of VDD and VSS in ICC2
Replies
3
Views
337
ThisIsNotSam
T
U
  • Locked
  • Question
[SOLVED] What are the steps that semiconductor companies perform to design digital ASICs from scratch?
Replies
3
Views
819
Noor ul ain
N
B
  • Question
Can't find definition of decap cells on the .lib file.
Replies
2
Views
320
bidhanpoudel
B
M
  • Question
Why is 28 Transistor CMOS Design widely used in the industry?
Replies
9
Views
1K
D.A.(Tony)Stewart
J
  • Locked
  • Question
[SOLVED] How to simulate a SRAM from MC2?
Replies
2
Views
634
Jordon
J
O
  • Question
drc error
Replies
6
Views
882
dick_freebird
D
R
  • Question
TSMC 0.18um dummy insertion only covers partial area
Replies
5
Views
958
ThisIsNotSam
T
M
  • Question
Verilog/VHDL Verification Assistant
Replies
9
Views
1K
MrCiffa
M
B
  • Locked
  • Solved
[SOLVED] Signal coming as undefined in verilog behavioral simulation
Replies
2
Views
820
bongosontan
B
Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…