Digital oscilloscope Project

[ME]

pc oscilliscope scematic

I'm focusing on input amplifier. If we use other power supply we can deliver +/-5V on opamps that have better characteristics.

We can do this from USB as well if we choose to. +-5V was in the orignal design but was removed because it wasn't nessasry. Now we have found out it might be a good idea anyway, we can just implement it again.

 

[ME]

digital oscilloscope forum

What about using OPA355/2355/3355 or OPA356/2356 as input buffer and supply it from small +-2.7V LDO regulators.

FEATURES

 UNITY-GAIN BANDWIDTH: 450MHz

 WIDE BANDWIDTH: 200MHz GBW

 HIGH SLEW RATE: 360V/µs

 LOW NOISE: 5.8nV/√Hz

 EXCELLENT VIDEO PERFORMANCE:
  DIFF GAIN: 0.02%, DIFF PHASE: 0.05°
  0.1dB GAIN FLATNESS: 75MHz

 INPUT RANGE INCLUDES GROUND

 RAIL-TO-RAIL OUTPUT (within 100mV)

 LOW INPUT BIAS CURRENT: 3pA

 LOW SHUTDOWN CURRENT: 3.4µA

 ENABLE/DISABLE TIME: 100ns/30ns

 THERMAL SHUTDOWN

 SINGLE-SUPPLY OPERATING RANGE: 2.5V to 5.5V

 MicroSIZE PACKAGES

The max supply for OPA35x is +5.5V or +-2.75V.
You can get fixed 2.7V LDO regulators and use an adjustable negative regulator for -2.7V.

OPA355/OPA2355/OPA3355: https://focus.ti.com/lit/ds/symlink/opa355.pdf
OPA356/OPA2356 https://focus.ti.com/lit/ds/symlink/opa356.pdf

 

[E-design]

oscilloscope+schematic

Requirements for Input Signal Conditioning:

Designing front-end for a DSO is difficult. Here are some of the problems a designer faces:

1/ A 500MHz scope needs 1GHz of bandwidth with a clean step response.
2/ This BW must be obtained with 1MOhm input impedance!!
3/ No resonance's of components should be present up to about 5 x the BW (5GHz)
4/ Because of high input resistance and low capacitance, you can't use transmission lines (the way to handle high frequencies)
5/ You need to keep the components and layout very small
6/ This delicate circuitry needs to withstand high electrostatic discharges and input voltages.
7/ Most difficult is to have gain flatness from DC to some part of the operating BW

 

[monnoliv]

parallel port oscilloscope proposals

This circuit is not as good for us, see figure below (page 9 on the datasheet). For 2Vpp signal (in case of using +-2.7V), the signal begin to be distorded @ 10MHz. Even for 1Vpp we have distorsion that begin @ 35MHz.
Also, the non-inverting response has peaking, even with no output capacitor (first figure in the datasheet).

 

[monnoliv]

avr lcd oscilloscope project

Requirements for Input Signal Conditioning:

Designing front-end for a DSO is difficult. Here are some of the problems a designer faces:

1/ A 500MHz scope needs 1GHz of bandwidth with a clean step response.
2/ This BW must be obtained with 1MOhm input impedance!!
3/ No resonance's of components should be present up to about 5 x the BW (5GHz)
4/ Because of high input resistance and low capacitance, you can't use transmission lines (the way to handle high frequencies)
5/ You need to keep the components and layout very small
6/ This delicate circuitry needs to withstand high electrostatic discharges and input voltages.
7/ Most difficult is to have gain flatness from DC to some part of the operating BW

Have you seen our input stage here: **broken link removed**

We're looking now for the point 7. Can you help us?

 

[ME]

oscilloscope 100mhz 20msps digital

We're looking now for the point 7. Can you help us?

I would suggest to use OPA657 or OPA656 and create +-5V from the 3.3V supply. Then we don't need the -3.3V supply anymore.

OPA657 and OPA656 looks like the best opams for the purpose found so far.

 

[simce]

build oscilloscope digital

I would suggest to use OPA657 or OPA656 and create +-5V from the 3.3V supply. Then we don't need the -3.3V supply anymore.

OPA657 and OPA656 looks like the best opams for the purpose found so far.

This is what i was talking about. Are there samples for these chips?

 

[ME]

pvt312 eagle

I would suggest to use OPA657 or OPA656 and create +-5V from the 3.3V supply. Then we don't need the -3.3V supply anymore.

OPA657 and OPA656 looks like the best opams for the purpose found so far.

This is what i was talking about. Are there samples for these chips?

Just click at "Request Samples" here:
https://focus.ti.com/docs/prod/folders/print/opa656.html
https://focus.ti.com/docs/prod/folders/print/opa657.html

 

[E-design]

schematic digital scope

We're looking now for the point 7. Can you help us?

I only have experience with designing input stages with split path using LF opamp to handle the DC conditions and FET stage to handle the HF-AC part. The 2 signal paths are then combined to give a smooth transition from DC to AC. This was the way input stages were designed before very high BW opamps came along. It had a few advantages. I have included a typical design just for interest.

I will observe and comment when I think it will be of any help.

 

[monnoliv]

dso-220

Thank you for your contribution.
But I can't see the advantage of splitting AC and DC part. Do you have a higher input voltage range with this circuit ? Don't you need a ladder (attenuator) ? What about output impedance ?
Regards,

 

[artem]

pc oscilloscope be project

Is it feasible to insert discrete amplifier after opamp , so opamp will be used to amplify signal up to 1v and discrete part will up it to ADC input range . That way you can still use OP355 or similar for input stage .

 

[ME]

pvt412 eagle

Try to check out these MOS op-amps from STMicroelectronics.
They all have very high input impedance and input bias = 2pA.
They can all run at +-3.3V and all have seperate offset adjustment.
www.st.com/stonline/bin/sftab.exe?d...1_nom=&le-XJG111_nom=&sortcol.x=8&sortcol.y=4

Common features:
* Supply Voltage ±3 to ±6 V
* VERY LOW INPUT CURRENT : 2pA typ
* STANDARD PIN OUT
* Offset bias adjustment

TSH11: www.st.com/stonline/books/pdf/docs/2473.pdf
* GAIN BANDWIDTH PRODUCT : 120MHz
* UNITY GAIN STABLE
* SLEW RATE : 150V/µs

TSH151: www.st.com/stonline/books/pdf/docs/4465.pdf
* LOW DISTORTION
* GAIN BANDWIDTH PRODUCT : 150MHz
* UNITY GAIN STABLE
* SLEW RATE : 200V/µs
* VERY FAST SETTLING TIME : 70ns (0.1%)
* VERY HIGH INPUT IMPEDANCE

TSH31: www.st.com/stonline/books/pdf/docs/2474.pdf
* GAIN BANDWIDTH PRODUCT : 280MHz
* GAIN OF 2 STABILITY
* SLEW RATE : 300V/µs

TSH321: www.st.com/stonline/books/pdf/docs/2328.pdf
* LOW DISTORTION
* GAIN BANDWIDTH PRODUCT : 300MHz
* GAIN OF 2 STABILITY
* SLEW RATE : 400V/µs
* VERY FAST SETTLING TIME : 60ns (0.1%)
* VERY HIGH INPUT IMPEDANCE


What do you think of these op amps as input buffers?

 

[E-design]

chocbar.demon.co.uk

Thank you for your contribution.
But I can't see the advantage of splitting AC and DC part. Do you have a higher input voltage range with this circuit ? Don't you need a ladder (attenuator) ? What about output impedance ?
Regards,

Remember this was done because in my time when we had no such fast opamps like today. It was convenient to have the opamp do the precision DC and LF work and at the same time handle the bias for the FET. You have better options now.

The circuit is only the impedance converter stage. I have not drawn in the attenuators before this. Output impedance will be low and designed to match the stage it is feeding. There were many variations of this design.

 

[ME]

pic18f4550 usb scope

The circuit is only the impedance converter stage. I have not drawn in the attenuators before this.

But I can already see an input impedance of 1Mohm in your circut (2*500kohm). Did you have more inpedance in front of this circuit?
I thought th input impedance should be 1Mohm.
What kind o attenuator was in front of it?
Can you show a schematic of that too?

 

[E-design]

avr osilloscope lcd

You are right. The input attenuator is a high impedance type with typical ratios 1, 10, 100, 250 etc.

Sometimes the attenuator arrangement is split between the input and output of the impedance convertor. They switch at the same time of course. This arrangement starts to be troublesome above a few hundred MHz because of parasitics of the switching contacts etc.

Another way (more complicated but better) is to have fixed capacitive dividers on the AC side (the FET buffer needs to be duplicated) and then by switching the feedback resistor to the opamp you get the required DC ratio. (this is getting complicated to explain) I will make more drawings when I have more time. For those who still follow...

The unwanted paths on the AC can be killed by switching pin diodes on the gate of the FETS, leaving only the AC to pass through the un-switched (wanted) one. The advantages are that you have switching on the AC side without introducing large capacitance changes (+-0.1pF) for the pin diodes and you can use semiconductor switches in the LF path. This way you eliminate any relays, switches in the input path as well as the parasitic effects that come with it with high frequencies. This concept was used in high performance Tektronix scopes from the early 90's.

Something else..

One thing I have not noticed in your guys design is a BW limit function. This is a very important feature. (maybe I missed it in the discussion)

 

[ME]

digital oscilloscopes for transistors

One thing I have not noticed in your guys design is a BW limit function. This is a very important feature. (maybe I missed it in the discussion)

No, I don't think this have been dicussed yet, I was thinking about this earlier because I have seen some scopes has a 20 MHz BW limit I think.

I'm not sure at wich frequency the BW limit should be, I only know from experience that some LF measurements are better if you activate the scopes BW limit.

Will it be enough to implement this as a 1st order filter at the input buffer?

Have you been working at Tektronix E-design?

 

[E-design]

projects with the oscillioscope

Have you been working at Tektronix E-design?

Not directly..but that is another story

Normally the BW limit is at 1/5th of the full BW. I will do the limiting after the input stage where you have lower impedances to work with

 

[ME]

dso input stage

Normally the BW limit is at 1/5th of the full BW. I will do the limiting after the input stage where you have lower impedances to work with

Thanks
The scope I remember had a 20MHz BW limit was a 100MHz HP / Agilent scope. This is excactly 1/5 of the BW as you said was the norm.

This DSO is planned to have a BW of 50MHz, so that means we should have a 10 MHz BW limit.

 

[E-design]

pc based oscilloscope project for be

It is also good to have an average function when making measurements on noisy signals. This can be implemented in SW later.

Is the 50MHz repetitive sampling? This means only 5MHz single-shot capability. You need also an anti aliasing detector to know when you are trying to sample a input frequency that is too high.

**broken link removed**

One common problem is capturing an fast event on a slow sweep speed. Then you need to employ peak detect. Here is a link with a short description that saves me a lot of typing.

**broken link removed**

 

[monnoliv]

dso mhz fifo

What do you think of these op amps as input buffers?

All these IC have an input common range of -Vcc to +Vcc - 3 !!!
I think that NO supplier is able to design a +-3.3V supplied FET opamp with input range of about +-2V.
Never mind I'm looking for high efficiency switchmode devices to create +- 5V with 3.3V

I will make more drawings when I have more time. For those who still follow...

We wait impatiently... :wink:

I will do the limiting after the input stage where you have lower impedances to work with

Ok but as Me ask, is a one order filter is enough ?

Is the 50MHz repetitive sampling?

The sampling frequency is 100MS/s.

You need also an anti aliasing detector to know when you are trying to sample a input frequency that is too high.

I presume that it's implemented in the analog part. Is there a simple mean (and cheap) to realize this ?

One common problem is capturing an fast event on a slow sweep speed. Then you need to employ peak detect. Here is a link with a short description that saves me a lot of typing.

We need large storing memory to do this, for the moment it's accepted (but not fixed) that the storing memory is 1024x10x2 bits. The Idea to have external SRAM is interesting... and on the way (no?)

It is also good to have an average function when making measurements on noisy signals. This can be implemented in SW later.

The software is not an issue from my point of vue, the hardware is more complicated.

By the way, I always had a question about commercial DSO: how they can sample with 1GS/s (true sample, not repetitive) with entry level oscilloscope (then cheap) ???
If you check all available fast ADC, you have max 250MS/s (not cheap). The solution of using 4 x 250MS/s ADC each with sampling delayed is expensive, then ... what is the trick ?