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Digital oscilloscope Project

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dso input amplifier 300mhz schematic

Here is a interesting article

About sampling rate:

Chuck Saxe is Engineering Manager of Tools Business Unit, Tektronix, Inc.

What is sampling rate and why is it important in the selection of test and measuring equipment?

What is sampling rate? Furthermore, why is it important? The answers to these questions should be understood so that accurate troubleshooting information can be obtained from available test and measurement instruments in commercial and industrial field service.

Before we answer these questions, let's discuss the basics of digital and analog technologies.

Analog versus digital sampling technology

Digital technology is rapidly replacing older analog technologies, both in equipment control systems and in the test instruments we use for troubleshooting, servicing, and calibrating these systems. Digital storage oscilloscopes are replacing their analog counterparts in many applications because they offer many advantages, such as automatic measurements, single-shot capture of intermittent electrical signals, memory storage, and hard-copy output. Also, the continual advance of digital circuit integration has produced extremely lightweight hand-held oscilloscopes and other related waveform-display tools that are well suited to portable use in commercial and industrial field service and maintenance.

Digital signal capture and display technology, however, does have certain limitations compared to analog technology. The most important limitation is related to sample rate.

Analog technology. Analog instruments work with continuously variable voltages. For example, an analog oscilloscope works by directly applying an input voltage to an electron beam that is moving across the oscilloscope screen. The voltage deflects the beam up and down proportionally, tracing an image of the input waveform, as shown in Fig. 1, on the screen. This gives an immediate and continuous picture of the waveform.

Digital technology. Digital instruments work with a series of voltage samples that are represented by discrete binary numbers. As such, a digital storage oscilloscope (DSO) samples the waveform, or measures it, at discrete points in time and uses an analog-to-digital converter (ADC) to convert these measured voltages into digital information (or "samples"). The DSO then uses this digital information to reconstruct the waveform on the screen, as shown in Fig. 2. In general, the faster the sampling rate, the more accurate the representation (waveform display) of the measured input signal.

This relationship can be compared to your PC display screen: newer VGA displays provide a much better representation of graphic images than older CGA screens of several years ago because they use many more pixels (or "samples") to construct the image.

Sample rate and bandwidth

The most familiar specification frequently used to gauge the performance of oscilloscopes is bandwidth. How does bandwidth relate to sample rate? Well, these two features are indeed related, but not always in a clear or direct dependency. This can lead to confusion when trying to interpret specifications from different oscilloscope manufacturers. The reason for this potential confusion is that several different sampling methods are used by different manufacturers. This variance is also from model-to-model.

To create a waveform accurately, a DSO must gather a sufficient number of samples relative to a trigger. In theory, a digital scope needs more than two samples per sine wave period (one full cycle of a regular waveform) to reproduce a sine wave. Otherwise, the acquired waveform will be a distorted representation of the input signal. This requirement usually limits the maximum signal frequency that a digital scope can acquire in real-time. Because of the limitation in real-time acquisition, many DSOs specify two bandwidths: repetitive-signal (or analog) bandwidth and real-time bandwidth.

The repetitive-signal bandwidth represents the highest-frequency sinewave signal that the scope's input circuits can accept with three decibel maximum attenuation (the point where distortion becomes unacceptable). It's important to note that this frequency limit applies to repetitive waveforms (signals that repeat in a regular and reliable fashion).

The real-time bandwidth, in contrast, defines the highest frequency sinewave that a DSO can capture by sampling in a single pass, using a single trigger. This is also sometimes called the single-shot bandwidth.

Is there more than one kind of bandwidth? The answer to this question lies in the two methods of sampling that are used in different scope designs: equivalent-time sampling and real-time sampling.

Equivalent-time sampling. The equivalent-time sampling method allows a DSO to have a bandwidth that is higher than its sample rate, which in fact many DSOs do. For instance, one popular DSO has a sample rate of 25 MS/s (mega-samples per second), but an analog bandwidth of 50 MHz. Because the sample rate must be more than twice the maximum signal bandwidth to build an accurate waveform, equivalent-time sampling must be used in this scope's design. The scope uses a series of successive trigger events to gradually build up a picture of the waveform. With each trigger, another set of samples are added to the picture, until enough samples have been collected to "fill in the blanks" so to speak and meet the Nyquist requirement for minimum number of samples required.

In equivalent-time, a slower, lower-cost digitizer can be used to sample high-frequency signals. This is because the samples are collected over time and by capturing multiple acquisitions.

Equivalent-time sampling should only be used when measuring repetitive signals. If there are intermittent glitches or single-shot events, they cannot be accurately captured and displayed using an equivalent-time reconstruction scheme because the events will probably not be captured at all. Even repetitive signals can be represented inaccurately if they vary over time, and the result can be image distortion that misrepresents the actual signal.

Real-time sampling. Scopes using the real-time sampling method must gather all the samples for a waveform from a single trigger event. This requires a higher sample rate to achieve the same bandwidth, as compared to an equivalent-time scope. This high sample rate is sometimes referred to as oversampling: a term meaning more than the minimum two samples are used per waveform period.

The benefit gained from real-time sampling is quickly realized when trying to view a signal that changes over time, as when making an adjustment in a piece of equipment or when trying to capture a single-shot or intermittent signal. Intermittent or transient events, which are common in equipment troubleshooting applications, must be viewable. Equivalent-time DSOs can capture single-shot events, but at speeds that are much slower. For example, a 50-MHz equivalent-time scope with a sample rate of 25 MS/s has an actual maximum single-shot bandwidth of only 10 MHz.

Other performance issues

Other performance characteristics tied to sample rate are waveform capture rate and a phenomenon known as aliasing. Aliasing occurs when the scope is not able to sample fast enough to accurately reproduce the input waveform. Here, the waveform displayed on-screen will appear to be a lower frequency than the actual signal, which can easily lead to misinterpretation. Special display modes such as peak detect (available on some scopes) can overcome this problem.

Waveform capture rate is the number of times per second the display can be updated with a new view of the input waveform. (Analog scopes have superior waveform capture rate since the electron beam drawing the trace is able to retrace and accept a new trigger with less hold off delay than a typical DSO.) Real-time DSOs can sometimes approach analog waveform capture rates, but equivalent-time sampling slows down the process because the waveform image must be built up over many acquisitions, which takes time.

Selecting an instrument

What does all this mean when selecting a test instrument? It means that your choice should be guided by the requirements of the application. If your measurements are on repetitive signals only, then an equivalent-time DSO may offer a cost-effective solution; here sample rate may be a non-issue.

If, however, you need to capture intermittent noise, glitches, or other single-shot phenomena, then a DSO with real-time capture and a high sample rate is the only choice to meet your performance requirement.


RELATED ARTICLE: WHAT IS THE NYQUIST SAMPLING THEOREM?

The mathematical rule governing proper sampling methodology is referred to as the Nyquist Sampling Theorem. The theorem states that "...the sampling rate must be at least twice the frequency of the highest frequency component in the waveform being sampled." In other words, for a complete determination of a specific waveform, the maximum separation in time given to regularly spaced instantaneous samples of a wave having a bandwidth W is equal to 1/2 Wsec.

Reference: The FFT: Fundamentals and Concepts, Robert W. Ramirez, Prentice-Hall, 1985 and the IEEE Standard Dictionary of Electrical and Electronic Terms.
 

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Thanks but I know this.
What about the specifications below ? Tek says that's real time sampling. How they can do such 1GS/s sampling so cheap ?
 

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Very often by "secret" and patented methods packed in a custom chip. If it was easy you could bet every manufacturer would be using it. As my work area was more analog design (10 years ago-retired now), I don't know the inside's of the latest digital techniques used today, but I am sure someone clever in this forum will know and be willing to share the basic principle.

And to answer a previous question "Ok but as Me ask, is a one order filter is enough" ?

As long as the filter is flat from DC upwards, a very simple LP filter is all that's needed. Typical a 2 pole filter will be used.
 

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E-design said:
Very often by "secret" and patented methods packed in a custom chip. If it was easy you could bet every manufacturer would be using it. As my work area was more analog design (10 years ago-retired now), I don't know the inside's of the latest digital techniques used today, but I am sure someone clever in this forum will know and be willing to share the basic principle.
´
Yes at this picture of Tektronix TDS2014, uploaded earlier in this very long thread, you can see it uses two custom made chips from National Semiconductor.
 

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How they can do such 1GS/s sampling so cheap ?
I can not remeber the name of the technology that is one of the first invented for such high speeds is call pipelined sampling. Well if you need 1G samples, you got 10 ADC's with sampling rate of 100MSPS and acquisition goes this way:
-first adc samples at time t=0; then second adc samples at time t=T; third adc at t=2T... tenth adc at t=10T, then first ADC samples again.
T=(number of adc's)/(Requred Sample rate[Hz]).
(number of adc's)=(Required sample rate[Hz])/(available adc sample rate[Hz]).
These samples are stored in separate memories and when complete sweep is made picture is displayed on the screen or send to PC. This way you can make fast acquisition as you can make fast controlling logic, that we can say today they goes in range od few GHz.
For super fast acquisition custom chip designs are made to minimize tray capacitances and length of connecting wires.
 

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Real time sampling is further complicated by the high speed memory required to store the waveform once it is digitized.

Measurement systems such as the Tektronix DSA 600 Series Digitizing Signal Analyzers, with sample rates to 2 GS/s and bandwidths to 1 GHz, have been optimized for capturing very fast single shot and transient events. These systems have the ability to sample input signals as fast as once every 500 picoseconds.
 

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ME said:
E-design said:
Normally the BW limit is at 1/5th of the full BW. I will do the limiting after the input stage where you have lower impedances to work with
Thanks
The scope I remember had a 20MHz BW limit was a 100MHz HP / @gilent scope. This is excactly 1/5 of the BW as you said was the norm.

This DSO is planned to have a BW of 50MHz, so that means we should have a 10 MHz BW limit.
I saw Tektronix uses 20MHz BW limit regardless of the maximum BW for these DSOs which have different maximum BW's ranging from 60MHz to 200MHz:
**broken link removed**

If I remeber correctly I have been working with 60 MHz & 100 MHz HP / Agilent scopes, 100MHz Hitachi scopes and 60MHz & 100 MHz Philips / Fluke scopes which all had 20MHz BW limit. + some other scopes I can't remember, one of the was a LeCroy 500 MHz scope I think, but I didn't use this $100.000 scope very much and can't remeber about BW limit, nice scope though, but I could probably never afford one of these "Rolls Royce" scopes for myself.
So it seems to be the norm to use 20MHz BW limit.
You could all check your scopes to check if this is true for different brands and models.
We should probably just use 20MHz as well, as it seems like most others do that.
Anyway, I think it should be fairly easy to change the BW limit after it is implemented, just by changing a capacitor and/or a resistor.
 

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The BW limit of 20MHz is used by most brands. I have a Tek scope 250MHz with switchable limits 20,100M. Then on my one Philips 350MHz only 20MHz is used. I once saw a limit on a scope of 10MHz. As ME said. it is not important at this time.

Also a FFT function will be nice (something to keep in mind for later) :)
 

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monnoliv said:
Thanks but I know this.
What about the specifications below ? Tek says that's real time sampling. How they can do such 1GS/s sampling so cheap ?

The sollution is "analog memory". It is a series of sample and hold elements on the same chip with a low speed adc. Often called ATWD (Advanced Transient Waveform Digitiser). Look for more info at: **broken link removed** . Unfortunatelly, this sollution seem to be available only for implementing in sillicon, not as a standalone products, and for this, you need big money to afford it. But, as Monnoliv said, for huge qty. it may become very cheap.

/pisoiu
 

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Hi!

I've readed your lasts very interesting discussions. 8)

Usign 10 parallel ADC's sampling in diferent times (T, 2T, 3T...) to get 1Gs is very dificult and expensive, because the layout of circuit is very important, the long of conections are a critical parameter, beacuase the delays of ns or ps are very important in these cases. You can compensate theses delays with roboclocks but is a paranoia!! :lol:

E-Design : You can obtain the FFT with C software (easy) in the PC, or implement the algorithm in the FPGA (or DSP) The scopes that I have seen (for PC) implement the FFT with a C software.

Best Regards. :roll:
 

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monnoliv said:
Thanks but I know this.
What about the specifications below ? Tek says that's real time sampling. How they can do such 1GS/s sampling so cheap ?

Maxim also makes a 1.5Gs/s 8bit ADC (Tektronix DSO's also has 8bit vertical resolution). The price is not listed for this ADC though, probably because nobody buys this in small quantities.

MAX108
±5V, 1.5Gsps, 8-Bit, Ultra High-Speed, A to D Converter with On-Chip 2.2GHz Track/Hold Amplifier
**broken link removed**
It uses Latched, Differential PECL Digital Outputs and comes in BGA housing, so it would not be suited for a home-made DSO.
 

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simce said:
How they can do such 1GS/s sampling so cheap ?
I can not remeber the name of the technology that is one of the first invented for such high speeds is call pipelined sampling. Well if you need 1G samples, you got 10 ADC's with sampling rate of 100MSPS and acquisition goes this way:
-first adc samples at time t=0; then second adc samples at time t=T; third adc at t=2T... tenth adc at t=10T, then first ADC samples again.
T=(number of adc's)/(Requred Sample rate[Hz]).
(number of adc's)=(Required sample rate[Hz])/(available adc sample rate[Hz]).
These samples are stored in separate memories and when complete sweep is made picture is displayed on the screen or send to PC. This way you can make fast acquisition as you can make fast controlling logic, that we can say today they goes in range od few GHz.
For super fast acquisition custom chip designs are made to minimize tray capacitances and length of connecting wires.

The MAX1180 dual 105Msps ADC which is used in this project actually consists of two two pipelined, nine-stage ADCs.
 

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ME said:
Maxim also makes a 1.5Gs/s 8bit ADC (Tektronix DSO's also has 8bit vertical resolution). The price is not listed for this ADC though, probably because nobody buys this in small quantities.
I've seen an estimated price in a press article, and if I remember correctly it was around $400. The date of the article was near the date of the release of this chip.

/pisoiu
 

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Hey!!

Don't forget the clock for 1Gsample. The FPGA must generate these clock... What is the main clock of FPGA in these case?? (double)??
What about the READ & WRITE times of SRAM....

The best scopes like LeCroy (20Gs) have an internal PC with PCI card with adquisition board, then is possible to do it!! :roll:

Best Regards.
 

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se06745 said:
Hey!!

Don't forget the clock for 1Gsample. The FPGA must generate these clock... What is the main clock of FPGA in these case?? (double)??
What about the READ & WRITE times of SRAM....

The best scopes like LeCroy (20Gs) have an internal PC with PCI card with adquisition board, then is possible to do it!! :roll:

Best Regards.

I do not think it is possible to generate 1GHz clock with FPGA, at least not with jitter requirements demanded by a high performance ADC. Clock jitter means conversion error, and for a good conversion, clock jitter must be under 5ps. The sample memory is another very complicated issue. Fastest synchronous sram available now can work at 500mhz. For this, databus from adc must be demultiplexed 1:2 (many ghz range adc have 1:2 demultiplexer included). Demultiplexing at higher factors means larger databus, and this is hard to layout in PCB. FIFOs also are limited at 250MHz (IDT).

/pisoiu
 

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se06745 said:
Hey!!

Don't forget the clock for 1Gsample. The FPGA must generate these clock... What is the main clock of FPGA in these case?? (double)??
What about the READ & WRITE times of SRAM....

The best scopes like LeCroy (20Gs) have an internal PC with PCI card with adquisition board, then is possible to do it!! :roll:

Best Regards.
Actually it is the other way around for these ultra high BW ADCs.
The 1.5GHz clock is connected directly to the ADC.
The ADC contains a 8:16 demultiplexer which divides the output data speed with two, so the output is 750MHz isntead of 1.5GHz, but 16 bit wide instead of 8 bit. The ADC generates a 750MHz DREADY signal which acts as output clock for the data. So the clock signal goes from the ADC to the controller and not the other way which is usual for slower clock speed ADCs.
 

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E-design said:
The BW limit of 20MHz is used by most brands. I have a Tek scope 250MHz with switchable limits 20,100M. Then on my one Philips 350MHz only 20MHz is used. I once saw a limit on a scope of 10MHz. As ME said. it is not important at this time.

Also a FFT function will be nice (something to keep in mind for later) :)

One little question . Does the Tek's 20 MHz bandwidth specify 2% accuracy measurement bandwidth as it is described in https://www.tek.com/Measurement/scopes/selection/pdf/55W_13768_1_band.pdf
or it is max measured freq ?
 

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se06745:
That's why i said for such a design custom silicons are made. Making design and production for about 1.000.000 pcs can reduce cost per peace a lot.
----------------------
About bandwidth: For now it is not that trivial to decide the frequency range of BW reduction circuit. This can be altered later. :idea:

Please stop theoretising about technologies that can not be implemented in home made DSO that has to be as cheap as it can but with needed characteristics. Lets concentrate on develpment of best DSO that we can make. :wink:

First we must concentrate on input amplifier stage, VGA, and ADC. I think that monnoliv's solution is improved since last revision. I suggest that we use OPA656_7 as replacement of AD8066, and make VMAG signal directly from DAC and not through transistor. This can be made using additional DAC for this purpose. REF output from sugested ADC has noise of 450uV that will be amplified inside VGA and can produce unwanted noise on output signal. Suggested ADC is a good chice.
If other voltages that this PWS supplies' are needed we can use other types of DC/DC convertors. Also I suggest use of additional SRAM of about 32kB that will be used for analog storage and storage of logic levels from logic analyzer.
 

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The MAX1180 dual 105Msps ADC which is used in this project actually consists of two two pipelined, nine-stage ADCs.
Yes i know, i've seen this information in datasheet of MAX1180.

In pipelined conversation for every ADC is used dedicaded SRAM with speed of single adc and not with speed of all adc's in to pipeline. This means that SRAM should be as fast as (Requred sample rate)/(number of adc's)
 

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Also a FFT function will be nice (something to keep in mind for later)
As se06745 wrote, it's a software issue and it's not a problem.

The sollution is "analog memory". It is a series of sample and hold elements on the same chip with a low speed adc. Often called ATWD (Advanced Transient Waveform Digitiser). Look for more info at: h**p://newport.eecs.uci.edu/~stuartk/spie-atwd.pdf . Unfortunatelly, this sollution seem to be available only for implementing in sillicon, not as a standalone products, and for this, you need big money to afford it. But, as Monnoliv said, for huge qty. it may become very cheap.
Very interesting... Analog memories are perhaps the custom chip that are at the input stage of the Tek scope showed by the link of ME.

and make VMAG signal directly from DAC and not through transistor
I'm not sure that it is necessary. The purpose of the GAIN_BOOST signal is to have the full range of the VGA gain. If you connect another DAC at the VMAG input, the two signals will be redondant (overlap on the gain).

If other voltages that this PWS supplies' are needed we can use other types of DC/DC convertors.
Done, I've to upload schematics
 

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