Digital oscilloscope Project

[ME]

xc9572 tutorial

Also I suggest use of additional SRAM of about 32kB that will be used for analog storage and storage of logic levels from logic analyzer.

But the point from the beginnig of this topic was to use an FPGA with internal RAM to avoid using external RAM, this was discussed a long time ago. Why do you suddenly want to use external RAM again?
Wouldn't it be better to use a CPLD instead of an FPGA if external RAM should be used as mentioned earlier in this topic?

 

[simce]

adc8060 осцил

But the point from the beginning of this topic was to use an FPGA with internal RAM to avoid using external RAM, this was discussed a long time ago. Why do you suddenly want to use external RAM again?
Wouldn't it be better to use a CPLD instead of an FPGA if external RAM should be used as mentioned earlier in this topic?

As I said in the beginning "I'm complete beginner in CPLD and FPGA designs" I thought that FPGA that is chosen has enough RAM for logic analyzer and DSO function. But during the development of DSO i've read some more information about this technologies and i think CPLD is good choice. One of the previous messages from monnoliv:

We need large storing memory to do this, for the moment it's accepted (but not fixed) that the storing memory is 1024x10x2 bits. The Idea to have external SRAM is interesting... and on the way (no?)

told me that we can have only 1024 samples. For DSO maybe it is enough (especially for event single triggered graphs) but for logic analyzer I think it is not enough. By the way what is the price for chosen FPGA compared with CPLD+RAM?
I'm using 16ch logic analyzer right now with 64k samples per channel. I think that this is more that most of us will ever need but for protocol analyzing it is good value. I think that we should use at least 4x16kB RAM for both channels and for logic analyzer( DSO will use 2x16kB per channel for 10bit per sample or someone can put only 1x16kB per channel for 8bit per sample, and logic analyzer will use 16ch*32kB for samples )
But, guys, please let we start from somewhere and then we can continue. This is confusing discussion where we are all telling some things over and over. For the new readers of this topic, please read all replies from the beginning.
First, we must concentrate on input amplifier and ADC. For now it is not that important if we are using CPLD, FPGA or something else (we have not decided what kind of input amplifier should be used). In Elektor electronics' magazine (february 2003) is presented logic analyzer for 40MSPS where is used triggering logic made of simple standard logic circuits that is controlled by MCU used for data transfer to PC. This is interesting design from where we can learn something.

 

[monnoliv]

+oscilloscope +project

First, we must concentrate on input amplifier and ADC. For now it is not that important if we are using CPLD, FPGA or something else (we have not decided what kind of input amplifier should be used). In Elektor electronics' magazine (february 2003) is presented logic analyzer for 40MSPS where is used triggering logic made of simple standard logic circuits that is controlled by MCU used for data transfer to PC. This is interesting design from where we can learn something.

Ok for input amplifier, I've to check the devices but for +- 5V supply, there are many good ones.
For the external SDRAM: you've to keep in mind that using external RAM cost at least 32 I/O pin, then I'm afraid that the logic analyser/generator will be reduced to only 8 bits. Don't forget that the logic analyser is a +, we don't have to reduce the performance of the DSO for it. Then if one find that using external SDRAM require only a drop of a SDRAM chip (no change for other circuit) then the logic analyser will be reduced. Historicaly, the logic analyser/generator was born with the free I/O pin of the FPGA.

Dead line for the design (because we have to make choice, there are a lot of solutions, we need one):
Analog part:
- choose the FET buffer (constraint: the 0.1dB flatness range)
- check the total input buffer noise to see the max sensitivity
- find an agreement for diff amplifier (noise) and VGA (if not already done)
- BW limitation
- ESD ???
- write the (theorical)specification of the input stage with all the components choosen for the input stage (and just for the fun, compare our spec to other PC scope, like pico scope).
Then the analog part is locked (until first real test).
Time to do this and discuss : 1 or 2 weeks (objective)

Then the digital parts:
- Evaluate SDRAM opportunity
- FPGA is fixed for me: EP1K30TC144 (but can be discussed of course)
- Some change to be done for optoisolators, evaluate JTAG with FT2232C, fast serial interface, ...
- USB1.1 is fixed for me (ok ?)
Time to do this and discuss : 2-3 weeks (objective)


Then software part...

 

[monnoliv]

ad9215 schematics

Hello all,

Input buffer: OPA656 (or OPA657, can be exchanged after tests)

Opportunity of external RAM:
- SDRAM are difficult to manage, one needs specials VHDL cores to interface with (and it takes FPGA ressource). Can't handle directly 20 bits (2x10), we must use 32 bits.
- FIFO: 64Kx36bits (72V36102, IDT), +-100$ (for comparison, that's +- the price of the ALTERA cyclone EP1C12 , 12Kx20bits embedded).

Comments ?

 

[se06745]

tlc5540 oscilloscope

Hi!
You can find (whit google) verilog code to implement the SDRAM control.
With PC SDRAM 133MHz (Fast & cheaper memory 128MBytes 48? or less)
And you can work in special MODE (like burst mode) to read & write data very fast.
If Data Bus is 32 Bits you can write 10+10 that you need.

Only problem is implement the control of SDRAM, but like I have said you can find free code (for some FPGAs, not all).

Best Regards!!

 

[monnoliv]

digital oscilloscope mk1

Only problem is implement the control of SDRAM, but like I have said you can find free code (for some FPGAs, not all).

I'm not an expert in SDRAM. Then Ok for the code but what happens if something in the design related to SDRAM doesn't work ?
Concerning SRAM, I've just read some datasheet from Samsung and there is a big problem: the consumption (200mA for 128K*32 for example).

 

[monnoliv]

c8051f320 ad　oscillo

Here is a first calculation of the input noise (ladder + buffer):

Contribution of VnR1 and VnR2:
VnR1 and VnR2 are thermal resistors noise that are BW cutted thanks to R1-C1 and R2-C2 then one neglet their contributions.
Contribution of InOP:
InOP - is injected into R3 that is a small value -> neglected
Contribution of VnOP:
VnOut = VnOP
Contribution of VnR3:
VnOut = VnR3
Contribution of InOP +:
BW cutted also thanks to R2-C1 (R2//R1 = R2)

Then VnOut = sqrt( sq(VnR3) + sq(VnOP) )
VnR3 = 2.2n V/sq(Hz)
VnOP = 7n V/sq(Hz)
=> VnOut = VnIn = 7.3n V/sq(Hz)

For 50MHz BW, Eq. input noise: 52 µV
For 100MHz BW, Eq. input noise: 73 µV

Let me know if something is wrong,

 

[Sobakava]

www.soudez.be dso

for using SDRAM with FPGA take a look to www.xess.com it works.

 

[presto]

digital oscilloscope projects

Hi, guys,

Any idea about the DSO software (not the firmware)? It there some kind of open source available? I tried www.sourceforge.com but they are platform specific. I'm think something in Java, so it's cross platform and easy to build good GUI.

cheers

 

[ME]

jyetech oscilloscopes

Hi, guys,

Any idea about the DSO software (not the firmware)? It there some kind of open source available? I tried www.sourceforge.com but they are platform specific. I'm think something in Java, so it's cross platform and easy to build good GUI.

cheers

You can also use LabVIEW to create the software.
https://www.ni.com/labview/

Some high-end stand-alone DSOs from Tektronix has built-in LabVIEW:

LabVIEW Running on Tektronix Open Windows Oscilloscopes (Multimedia Demo (4 min)):
https://digital.ni.com/demo.nsf/web...986256C8E007BEECB?OpenDocument&node=157200_US

Streamline Your Design Process with NI LabVIEW and Tektronix:
**broken link removed**

 

[dainis]

ds1077 problems

**broken link removed**

Advanced transient waveform digitizers.

A series of multi-channel transient waveform digitization integrated circuits with up to 5 GHz sample rates and parallel
10-bit digitization has been designed, tested, and fabricated in large quantities. The current CMOS circuit uses four
arrays of 128 fast switched capacitors per channel to record four parallel analog transient inputs. Triggering and clocking
is provided by a current-mode-adjustable asynchronous active delay line that uses look-ahead to generate 128 4-way
interleaved clocks without the need for external high-speed clocking. After transient capture, each channel is fed into
128 parallel 10-bit analog to digital converters for fast, channel-parallel digitization, followed by digital readout. The fast
triggering and waveform capture, channel-parallel digitization and convenient word-parallel digital readout results in a
responsive and low dead-time system. Acquisition sample rates range from ~50 kHz to ~3 GHz. Analog input bandwidth
is approximately 350 MHz.

 

[monnoliv]

digital oscilloscope theory adc

A series of multi-channel transient waveform digitization integrated circuits with up to 5 GHz sample rates and parallel
10-bit digitization has been designed, tested, and fabricated in large quantities.

Can we have samples for this "custom" IC ? Is it foreseen to release a commercial version ?

Regards,

 

[pisoiu]

fpga as an oscilloscope

Can we have samples for this "custom" IC ? Is it foreseen to release a commercial version ?

I've spent many hours looking for such IC, but I've found nothing. It seem that it is used only as a custom sollution for those who can afford it, like tek and other osc manufacturers. The technology is promising, it allows fast acq. rates at low cost, even if the depth of acquisition is a problem.

/pisoiu

 

[simce]

max153 audio circuits

Let stay on 100MHz version to see what are common problems associated with this design, then we can go on advanced and faster solutions. But i think that for 1Gsamples or faster integrated solutions are needed because of delay through PCB for these speeds!

 

[beshan]

handy oscilloscope pc pcb

Hey everyone I am kinda new to this forum. I followed most of the discussions, and was just wondering if this is still an active project ?

thanks !

 

[rauol]

circuit diagram of dso

8) Does anybody have circuit diagrams of High Voltage Differential Probes
P5200 • P5205 • P5210 from Tektronix

 

[monnoliv]

projeto osciloscopio usb

Hi all,

Of course this project is still on the way. But now, it's holiday and several "DSO Team" members are in vacations or take a rest (like me :wink. Then for the moment the development is in hibernation mode.

See you,

 

[KIG]

c8051f320 oscilloscope

Hi all,
ot is an interestin topic,
but what is the cost for building a DSO

 

[monnoliv]

oscilloscope input protection circuit

Hi all,
ot is an interestin topic,
but what is the cost for building a DSO

It depends of the final configuration. Up to now, for the PC version, I hope that 300€ - 400 € is enought.

 

[monnoliv]

cyclone oscilloscope

Hi everybody,

After more than a month of rest, here is the 6th revision of the DSO (register to see the schematics):

**broken link removed**

Regards,