Digital oscilloscope Project

[simce]

p5210 tektronix

What kind of spikes? Don't forget that you have C2-R10 in parallel with U5, they act as a short for spikes, no?

I ment spikes with Vpp=1000V, and duration of 0.5-1s. I was unable to find what is needed current that can damage the PVT. If it is small current than U5 will be damaged.
Maybe i sound a bit paranoic, but doing power electronic, i've seen few vaporized input stages of good DSO's and similar instruments, used to measure small signals. But sometimes happens that "small signals" to become very high. Maybe no instrument can be made to override this situations? Or maybe not? OK. For now it is not that trivial to think about this problems. We can resolve them later.

Concerning the nonlinear capacitance of mosphet, the Idea is to have as small as possible voltage across inputs in order to have a relative constant capacitor (of +-170pf):

I was thinking about U6/U7.

Let's work a little bit more and be patient (btw, ME proposed to me a new solution that seems vgood).

OK. I'm very patient person . I just want to help make this project as good as ready made DSO's, and i want make it work at first ( i hate spending time fixing stupid erros i make during develpment ).

monnoliv:
I'm apsolute begginer in CPLD/FPGA designs , and this project has inspired me to start studying this technologies :idea: . So please tell me something about used FPGA in this project ( used development software, which language you are using, develpment/eval board...) so i can be in track with it!

 

[monnoliv]

hardware debugging of d flip flop using dso

What is the BandWidth of PVT312?? I have not seen nothing in datasheet.

In my opinion it's the capacitors that act as filter, depending on the way you implement the device. There are two capacitors: the first one is the one accross MOS (20pf-170pf), the second one is the input(LED)-output(MOS) capacitor (1pF).

You command the main gain with digital lines throught VGA IC.

That's not digital lines, that's analog ones (GAINx & GND_GAINx) there are output of the DAC U10.

The offset calibration or compensation where are?? Is digital too??

P1 & P2 are used for the calibration...

Why do you change input impedance???

??? Input impedance: the resistive part is 1M005 that's near 1M (and one can find the right resistors to have 1M000).

Maybe no instrument can be made to override this situations? Or maybe not? OK. For now it is not that trivial to think about this problems. We can resolve them later.

I'm afraid no (general purpose) instruments can sustains such voltages.

I'm apsolute begginer in CPLD/FPGA designs

So am I :lol: . Let me write you the simplest way to begin (that's my experience, not a general assertion):
- Browser the FPGA devices at Altera for example, just to know the differences between devices (for example the DSO FPGA has RAM storage, not all FPGA has RAM storage)
- Download the Quartus II Web edition from Altera.
- Choose the Tutorial and follow it step by step.
- Before learning VHDL or VERILOG, use the megafunction included with the software (megafunction are device optimised script in VERILOG or VHDL that build a specific function: FIFO, ADDER, MULTIPLEXER,...), the remaining parts can be drawn by schematics. Timing is shown by compilation and simulation (worst cases are shown without simulation), ...

 

[se06745]

tlc5540+oscilloscope

Hi!

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Quote:
You command the main gain with digital lines throught VGA IC.
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That's not digital lines, that's analog ones (GAINx & GND_GAINx) there are output of the DAC U10. (YES!!! I know)
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YES!!! I know YOU USE DIGITAL LINES TO CONTROL THE GAIN with DAC converts the DIGITAL inputs to ANALOG outputs......

--------------------------------------------------------------------------------
Quote:
The offset calibration or compensation where are?? Is digital too??
--------------------------------------------------------------------------------
P1 & P2 are used for the calibration...
--------------------------------------------------------------------------------

OK, But I think that isn't the best way to do it.

Best Regards!!!
:arrow:

 

[simce]

tlc5540 pic

--------------------------------------------------------------------------------
Quote:
The offset calibration or compensation where are?? Is digital too??
--------------------------------------------------------------------------------
P1 & P2 are used for the calibration...
--------------------------------------------------------------------------------

OK, But I think that isn't the best way to do it.

se06745:
Maybe you can propose another solution, and then we can discuss about it.

monnoliv:
Does Altera's development software supports both Verilog and VHDL? What is your preferance?

 

[se06745]

pc based digital storage oscilloscope mk3

Hi!

Well. I think that you need to configure the offset with the PC.
Put a digital potenciometer with Adder OP configuration. ¿?
The Vref should be very stable.

Thank's

 

[monnoliv]

pc-oscilloscope schematic

Does @ltera's development software supports both Verilog and VHDL? What is your preferance?

Yes, it support VHDL, VERILOG and AHDL (Altera proprietary langage). I've a preference in VHDL since I've a little knowledge with this langage, but I can learn VERILOG too.

Put a digital potenciometer with Adder OP configuration. ¿?
The Vref should be very stable.

I think also that we've to use automatic offset canceling and, as you write, why not with a digital potentiometer. But take care with the price.

 

[simce]

dspic30f4012 adc oscilloscope

On eMule i'v found few documents that seems to be a service manuals for Tektronix. I've downloaded all of them, but they are service manuals for entry level service personell, and no schematics are present in that document (Tektronix_TDS200 series SM.pdf file). There is anoter document: Oscillo Tektronix TDS210_sp.pdf which is password protected. So if anyone has knowledge or tool to find the password please dowlnoad file from eMule or i can send it to you or post on eboard somewhere. Maybe this is service manual that contains some usefull schematics.

 

[se06745]

osciloscpe project

It's so dificult because the length of password can be long!!

You can find programs to crack it but needs a lot of time can be hundred of years.....

 

[simce]

lmx9838 +price

It's so dificult because the length of password can be long!!

You can find programs to fix it but needs a lot of time can be hundred of years.....

I know that brute-force methods can last forever. I ment if there is some more efficient method?! :?:

 

[se06745]

ad8063 spice model

I don't know!!! I think is more easy to study and argue your own schematic.

 

[se06745]

handheld oscilloscope+schematics

Hi!

I have downloaded two decript programs. Please send me protected PDF file, and I try to deprotect it.
my e-mail : se06745@salleurl.edu

thanks for all.

 

[simce]

cmccord.co.uk/fyp/final

Has anyone suceeeded in decryption of file and what is resulting file?

 

[se06745]

oscilloscope design front end

Yes

I have used Advanced PDF recovery password v2.2. The key search algorithm. In three days I find a Key number 12239 that corresponds with ed 11 cf 2f e3 (hex key)
Well All ok!! But when I try to decript it with the Advanced PDF recovery password program these give me OK Decript file Succefull but not decript it. I don't know if is a bug of the program. You can try to decript it with these key.
Another program can be guaPDF but I have de DEMO program.

Best Regards!

 

[ME]

www.usb-osc.norod.ru/

Yes

I have used Advanced PDF recovery password v2.2. The key search algorithm. In three days I find a Key number 12239 that corresponds with ed 11 cf 2f e3 (hex key)
Well All ok!! But when I try to decript it with the Advanced PDF recovery password program these give me OK Decript file Succefull but not decript it. I don't know if is a bug of the program. You can try to decript it with these key.
Another program can be guaPDF but I have de DEMO program.

Best Regards!

The key "ed 11 cf 2f e3" works fine if you remove the spaces: ed11cf2fe3
But I only have a demo version of Advanced PDF password recovery pro v2.2, so I'm only allowed to UnEncrypt the three first pages of the 26 pages.

 

[se06745]

firewire osci

Yes. Now I have downloaded the demo program and decrypt the document. Well
It`is spanish presentation document (not eschematics)


Best Regards

 

[monnoliv]

digital oscilloscope mcu

Hi guys,

I've uploaded the 5th revision of the DSO @
**broken link removed**

You'll see that the input stage has been simplified in order to cancel the (variable) influence of the capacitance photomos. But the dynamic is still quite good, let us know.
Some others changes:
Input stage
Offset VGA
Gain VGA (+-65dB)
Digital connector
Programmable clock
Optoisolator
Supply (no more +5V @ the isolated secondary)
+ some other minors changes

ME and me :lol: are working on it but as I can see (over 14000 Views) a lot of people are interested. Then don't hesitate to suggest something for the scope (hints, remarks, ...).


Regards,

 

[simce]

tiepie usb to parallel

monnoliv:
As i can see you are still using AD8066 as input buffers. I've sugested other opamps that i think has better characteristics to ME and few to the forum. Have you take a look on them and what are you comments on them?

 

[monnoliv]

pc osciloscope schema

Ok, I'll check to use the AD8057_8 or OPA656 or OPA657.
Regards,

 

[simce]

instability ad8331

monnoliv and ME:
I must say that this is much improved version than previous ones. I took a closer look on the shematics and i have few notes/questions about it:
1. I think that RC or LC or pi filter should be used for REF_VMAG (it has noise of 450µV for 1,2V output that will interfere inside VGA).
2. Use of resitor and capacitor (RC filter) or LC filter on VDD of U5 and U6 to reduce digital noise from U5 and U6 injected into analog voltage during operation of DAC.
3. How FPGA is cofigured (only via USB/JTAG) or somehow else? Does it has internal configuration memory?
Regards,
Simce

 

[simce]

digital scope low frequency with dspic30f

Another question about PWS:
Power is drawn from USB, goes through TRACO DC/DC convertor and goes to 3.3VDGEN and to ITX5, but from where comes 3.3VDG? Does shorcut is supposed to be placed between 3.3VDGEN and 3.3VDG on ITX5?