Digital oscilloscope Project

[monnoliv]

project oscilloscope low frequency

Here is an updated version of the range of the input stage.

 

[monnoliv]

digital oscope +avr

Hi all,

I've finished a major upgrade of the DSO, a lot of enhancement +
- Input stage uses photomos
- 2x10bits 100MS/s ADC conversion
- µC no more needed for the PC version
- VGA amplification
- Logic analyser + pattern generator 32 bits

Thanks to advices and remarks from ME, the DSO is on the (good) way:

**broken link removed**

Regards,

 

[simce]

fpga based pc oscilloscope

Few notes about schematic (Input Amplifier):

1. U8 PIN4 (maybe to AGND)?
2. Low capacitance protection diodes from input of amplifiers to 3v3 and GND should be added?

Also i think that C1 and C2 shoud be increased to get better frequency characteristic for ultra low frequencies? I know that this is not good because maximum peak current of photomos is not big enough, but!

 

[ME]

oscilloscope project microchip

U8 PIN4 (maybe to AGND)?

Yes it should be connected to AGND.

Low capacitance protection diodes from input of amplifiers to 3v3 and GND should be added?

There is protection diodes inside the op-amp, you can read about it in the data sheet. I don't know if external capacitors are needed too, the input impedance from the BNC is quite high, 500kohm.

There is calculations of the input current/voltage which can be handled by the op-amp for a given input impedance, look at figure 55 in the data sheet.
Do you still think external diodes are required?

Anyway a diode should never be connected to GND as you say but to -3.3V. Otherwise you can't use the scope for AC voltages.

Also i think that C1 and C2 shoud be increased to get better frequency characteristic for ultra low frequencies? I know that this is not good because maximum peak current of photomos is not big enough, but!

How big do you think they need to be?

 

[monnoliv]

random repetitive sampling

Also i think that C1 and C2 shoud be increased to get better frequency characteristic for ultra low frequencies? I know that this is not good because maximum peak current of photomos is not big enough, but!

How big do you think they need to be?

I've made a SPICE simulation and I've about 10Hz cutt-off frequency for high pass. I think it's good enough, no?

Thank you for your remarks,

 

[monnoliv]

ad8330 spice

Here is the schematics of the simulation:

 

[simce]

jyetech dso

ME:
Yes, you are right about protection diodes, they should be tied to +\-3V3. Also you were right about internal protection diodes inside AD8066. At first I though that maximum current should be 30uA and not 30mA as said in datasheet across input pins through protection diodes inside OPAMP. Thank you for correction.
About C1 and C2.
monnoliv:
As I can see from schematic used for simulation, probe with resistance of 9M ohm is used, and as I know this is when probe is set to x10, what about when it is set to x1 position? I think that for this configuration at least 47nF should be used. 100nF is good value by my opinion. Another question: why 4.7n is used for C4 in simulation? Is this some parasitic capacitance of PVT317S? Tomorrow I'll run few simulations to see what happens when another values are going to be used.
Also I'm curious to know why AD8066 is used as first amplifier/buffer (it has gain of 1 V/V).
As I can see from it's datasheet it has 7MHz bandwidth within gain 2 and 0,1dB flatness. It has only 180V/uS slew rate on gain 2 (I can not find value for gain 1). It has ripple in frequency characteristic above 20MHz (figure 4). Noise of 7nV and input offset of 1.5mA.
I was comparing this OPAMP with MAX477 and it seems to me that MAX477 is much better choice.:
Slew rate: 1800V/us
Input offset: 0.5mV
Bandwidth:300MHz
Noise: 5nV
ESD:8000V (AD8066 has 1500V)
Small signal, 0.1dB gain flatness: 130MHz.
Good impulse characteristic..
Maybe there are other better opamps made for gain 1 and better characteristic than max477. I'll search for them as soon as i find some free time.
Regards.
p.s. As i can see every one is waiting for monnoliv and ME to make this project working! We all must help to make this DSO better than others present on the market! Because of this anyone's help is welcomed!

 

[ME]

a/d converter as oscilloscope

Thanks simce.

The Differential Input Impedance of MAX477 is only 1 MΩ, this is too little compared to the resistance of the ladder.

AD8066 is a JFET opamp with an Differential Input Impedance of 1000 GΩ || 4.5 pF. 1000 GΩ won't affect the ladder, but I don't know if 4.5pF will affect the ladder, what do you think?

This is the main reson why AD8066 is used.
It's hard to find high input impedance JFET opamps with such a high bandwidth as AD8066.
I haven't found any, but if anybody knows a better opamp for the purpose, please tell.
Most high bandwidth opamps are made for low impedance sources such as video signals.

How are the input stage of Oscillosopes usally designed?
Does anyone have an Oscilloscope schematic?

 

[pisoiu]

simple digital oscilloscope + bme

Dear friends,
This one is not straight related to Monooliv project, but is a serious problem in high performance DSO, and I would like to know your opinion about it.
Usually, the triggering system is made analogic in high performance DSO, the main element being a high speed comparator. When the DSO samples at speeds much higher than the speed of the aquired signal (meaning you have one or more samples for each element of vertical resolution you want to display), this problem is not a concern. But when you sample near or close to Nyquist rate, far less samples are available for displaying the waveform, and in this case linear or sin(x)/x interpolation should be implemented to fill up the gaps between real samples. But...when the triggering signal (regardless if it is one of the traces or externally) is processed analogically, the position in time between the trigger point and the first sample which occur after it, is not constant from one chosen frame to tne next one (only if the ratio between sampling signal freq. and acquired signal freq. is an integer). This difference will vary from one displayed frame to another, and I think it will cause instability in the displayed waveform if this error is not measured and if the waveform is not adjusted according to it. Any ideas about this?

/pisoiu

 

[monnoliv]

100 oscilloscope projects

Sorry pisoiu, I didn't seen your post before replying


Thanks simce for your remarks,

...why 4.7n is used for C4 in simulation? Is this some parasitic capacitance of PVT317S?

No no, it's a mistake on the schematics website (not in the simulation, 4.7nF is the good value).

what about when it is set to x1 position? I think that for this configuration at least 47nF should be used. 100nF is good value by my opinion

It doesn't matter for me (simulation) but make a simulation to be sure.

but I don't know if 4.5pF will affect the ladder, what do you think?

Yes, it affect the response now, because C3 is much lower then before (in the previous revision C3 = +-250pF, thanks I didn't see the problem). As C3 is lower, 4.5pF isn't negligible anymore (0.7 dB fluctuation on BW). One have to keep in mind that the input capacitor of the buffer (say Cx) is moving from 1/2 branch to 1/200 branch depending the position switch. Anyway, I see a solution to this problem: a resistor across the capacitor (about 5 meg). It correct the problem on the 1/2 branch. On the 1/200 branch these resistor-capacitor are negligible. Of course I've to recalculate the other ladder parts to still have 1Meg/20pF input impedance.

 

[monnoliv]

ad8331 pspice noise

Hi pisoiu,

Can the trigger signal at the output of comparator be latched with the sampling clock (edge triggering on the sampling clock for example) ? Then the signal at the latch output represent an other triggering signal (delayed regarding the first one) that is synchronised with the sampling signal. If one use this second triggering signal for displaying, no more jittering will occur, no?

Regards,

 

[ME]

oscilloscope project low cost

but I don't know if 4.5pF will affect the ladder, what do you think?

Yes, it affect the response now, because C3 is much lower then before (in the previous revision C3 = +-250pF, thanks I didn't see the problem). As C3 is lower, 4.5pF isn't negligible anymore (0.7 dB fluctuation on BW). One have to keep in mind that the input capacitor of the buffer (say Cx) is moving from 1/2 branch to 1/200 branch depending the position switch. Anyway, I see a solution to this problem: a resistor across the capacitor (about 5 meg). It correct the problem on the 1/2 branch. On the 1/200 branch these resistor-capacitor are negligible. Of course I've to recalculate the other ladder parts to still have 1Meg/20pF input impedance.

I'm sorry but I don't understand.
The 4.5pF capacitance I was talking about is the input capacitance in the opamp, I don't think you can put 5MΩ across this capacitance??
Across which capacitor do you wan't to put 5MΩ?

 

[pisoiu]

usb uscilloscope project

Hi pisoiu,

Can the trigger signal at the output of comparator be latched with the sampling clock (edge triggering on the sampling clock for example) ? Then the signal at the latch output represent an other triggering signal (delayed regarding the first one) that is synchronised with the sampling signal. If one use this second triggering signal for displaying, no more jittering will occur, no?

Regards,

Yes, true, applying this method give same results like triggering on digital signal (take samples, and when first sample is over or under a treshlod level, you consider that as trigger point). But when you trigger with external signal and/or when you want to measure the elapsed time between a trigger point (trace 1 or externally) and a certain event on trace 2 (for example), this method will affect your result. This is why triggering on digital output is not used too often. The clue is to measure the elapsed time between trigger point and the first sample moment. I've done this using a 2,2 GHz counter which starts to count at trigger point and stops at first sample. The counter is re-armed before every display frame. This method is also usefull when you want to acquire repetitive signals with freq. much higher than niquist rate.

/pisoiu

 

[monnoliv]

homemade dso

I'm sorry but I don't understand.
The 4.5pF capacitance I was talking about is the input capacitance in the opamp, I don't think you can put 5MΩ across this capacitance??
Across which capacitor do you wan't to put 5MΩ?

Why ? 4.5pF is roughly the input capacitor of the FET buffer. If you put a 5meg resistor in parallel with this cap (then in the input of the FET buffer, between the +in and gnd) you'll have a new ladder that is frequency equilibrated (flat response). Now if you switch to the 1/200 branch, input cap + resistor are negligible comparing to 4n7 and 5K.

In fact one have to take into account also the capacitance of the GND photomos switch that is far more bigger (I didn't see it) ! One have to find something.

Good night,

 

[ME]

fpga digital scope

I'm sorry but I don't understand.
The 4.5pF capacitance I was talking about is the input capacitance in the opamp, I don't think you can put 5MΩ across this capacitance??
Across which capacitor do you wan't to put 5MΩ?

Why ? 4.5pF is roughly the input capacitor of the FET buffer. If you put a 5meg resistor in parallel with this cap (then in the input of the FET buffer, between the +in and gnd) you'll have a new ladder that is frequency equilibrated (flat response). Now if you switch to the 1/200 branch, input cap + resistor are negligible comparing to 4n7 and 5K.

In fact one have to take into account also the capacitance of the GND photomos switch that is far more bigger (I didn't see it) ! One have to find something.

Good night,

That's what I was afraid you meant.
5Mohm from +input to GND would be a very bad idea.
This would be connected in parallel with 1Mohm in the ladder in /2 mode, this won't work.

Then you might as well use an opamp with a low input resistance.

 

[monnoliv]

circuit diagram to make oscillascope from pc

Then you might as well use an opamp with a low input resistance.

No because the low impedance of other opamp (non FET) isn't well known, and we have no means to act on it.
If you prefer, one can see this resistor as a correction that is part of the ladder in order to take into account the FET opamp input capacitance.
But ok, we have another problem with the 170pF capacitance of the GND photomos switch.

 

[ME]

mcu oscilloscope digital adc

If you do this you will change the input impedance seen from the BNC when you switch from 1/200 to 1/2.
The input impedance will no longer constantly be 1Mohm. If the input impedance isn't excactly 1Mohm you will get wrong measurements when you switch from 1:1 to 1:10 or 1:100 at the probe.
That's why this soloution is bad.

 

[simce]

usb fpga adc ghz oscilloscopes

What about:
PVT312 => Operating Voltage Range 0 to ±250 V(DC or AC peak) (from datasheet)
I think that U5 can be damaged with voltages spikes comming from input BNC (when U5 is in off state). What are your opinions about this? Also i was looking at figure 9? This is nonlinear capacitive load in input ladder.

I suggest that we make modular design of this DSO, and when we make something useful, we can change the input stage. For this, lets stay on simple input stage that contains no PVT devices and use simple switchers with low capacitance for AC/DC mode selection. In the beggining it is not that trivial to have 1mV/div. Gain of input stage can be adjusted by VGA opamp without need for switches and similar components.

About MAX477, i saw input resistance value, but i forgot that input ladder is with similar impendace. But if we use input stage that has low impendace on low side of ladder (about 100k) than this opamp can be used. This way we won't be able to sample small signals, but we'll have good freqency response.

Also we must consider that using opams in cascade (like this situation) resulting bandwidth is smaller than the opamp with lowest bandwidth.

I searched a while www.analog.com and i find (by my opinion) better opamp than AD8066. I think that AD8038 is better choice. Take a look AD8038 datasheet and comment on this.
Also take a look at AD8057_8, AD8055, AD8063...

 

[monnoliv]

o scope projects

I think that U5 can be damaged with voltages spikes comming from input BNC (when U5 is in off state). What are your opinions about this? Also i was looking at figure 9? This is nonlinear capacitive load in input ladder.

What kind of spikes? Don't forget that you have C2-R10 in parallel with U5, they act as a short for spikes, no?
Concerning the nonlinear capacitance of mosphet, the Idea is to have as small as possible voltage across inputs in order to have a relative constant capacitor (of +-170pf):
-For U5 in AC mode, the capacitor is negligible compared to C2
-For U8, voltage is +-500mV MAX
-For U6, U7 it can be a problem for sure.

I suggest that we make modular design of this DSO, and when we make something useful, we can change the input stage. For this, lets stay on simple input stage that contains no PVT devices and use simple switchers with low capacitance for AC/DC mode selection. In the beggining it is not that trivial to have 1mV/div. Gain of input stage can be adjusted by VGA opamp without need for switches and similar components.

We have to find a solution that gives at least an input stage that's equivalent to a commercial entry-level oscilloscope (and with automatic features). I think that we are not so far from the solution. One doesn't want to have a simple solution by facility, no? Let's work a little bit more and be patient :wink: (btw, ME proposed to me a new solution that seems vgood).

I searched a while www.analog.com and i find (by my opinion) better opamp than AD8066. I think that AD8038 is better choice. Take a look AD8038 datasheet and comment on this.
Also take a look at AD8057_8, AD8055, AD8063...

Ok, I'll check.

Thanks for your remarks simce

 

[se06745]

johan glaser dso

Hi!

I have seen your new design!!
What is the BandWidth of PVT312?? I have not seen nothing in datasheet.
You command the main gain with digital lines throught VGA IC. The offset calibration or compensation where are?? Is digital too??

Why do you change input impedance???

Thank's for all!! :lol: 8O