Digital oscilloscope Project

[ME]

johann-glaser.at/projects/dso

Why not to use ready development board? For example, many times discussed here Virtex2Pro board from Memec. 149$, V2Pro4 FPGA (more than 500 Kbits of internal BlockRAM), embedded PowerPC processor, USB and RS232 ports. It will allow to forget about all this troubles with PCB and soldering and concentrate on real DSO design.

Ace-X.

Are you talking about this board:
www.insight.na.memec.com/Memec/iplanet/link1/VirtexIIProLC_1.pdf

www.fpgajournal.com/news_stories2004/Mar/20040310_02.htm
www.us.design-reuse.com/news/news7352.html


According to Memec's web site, this board costs $195 and not $149.
**broken link removed**

Where can you buy this board for $149?

The Xilinx Virtex II Pro sounds like a very powerful FPGA with a Powerful IBM 400MHz PowerPC processor built-in!
Xilinx Virtex II Pro: www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-II+Pro+FPGAs
This should be more than enough for a LCD DSO.

A board with such a powerful FPGA and onboard LCD, USB, RS232 etc. for under $200 sounds like a bargain.

The kit could be used for other experiments than the DSO too, you could just attach another expansion PCB instead of the DSO analog frontend.


But maybe this soloution will still be too expensive compared to the DIY soloution with PCB, USB, MCU and a smaller FPGA?

 

[monnoliv]

jyetech.com

Hi all,

I invite you to see the third revision of the DSO @ **broken link removed**
Now:
* FT2232C in place (no more FT232BM)
* No µC needed for PC-DSO version
* 32 bits digital analyser
* only one connector to include the parts needed for the hand-held version

ToDo:
- Better protection circtuit for the digital inputs?
- Calibration circuit for the analog inputs.

Comments welcome and thank you ME and all for your advices.

Regards,

 

[davorin]

digital sampling oscilloscope

What are nowadays best available (and also payable ;o) ADCs?

Some other company than Maxim/ADI//NS providing >= 500MSamples @ 8 bit at an affordable price or even supplies samples?

 

[Ace-X]

project usb oscilloscope

According to Memec's web site, this board costs $195 and not $149.
**broken link removed**
Where can you buy this board for $149?

See posts by eltonjohn:



BTW, substitution of alphanumeric LCD to graphic LCD will let you to use the whole system as a stand-alone DSO. PowerPC can be used for LCD control and drawing.

Ace-X.

 

[se06745]

digital oscilloscope

Hi monnoliv!!!

I think your design need a DC compensation for the ADC input, as a DC adder to obtain the best ADC resolution range. It's necessary to put an adder configuration operational amplifier?
Furthermore you can put a 74ac244 to protect digital inputs for the logical analizer.

Best Regards!

 

[ME]

digital oscope with avr

@monnoliv

You have switched pin 3 and 4 of all the HCPL-063L double optocouplers, U13, U14 and U15.
The LEDs will never turn on.
**broken link removed**

 

[ME]

avr multikitb

Furthermore you can put a 74ac244 to protect digital inputs for the logical analizer.

I think you should rather use 74ACT244 (TTL tolerant inputs) than 74AC244.
Remenber to connect Vcc to 5V to make the inputs 5V logic tolerant, they can still interface with 3.3 V logic. The outputs will be 5V logic, but the FPGA inputs are 5V tolerant when the FPGA I/O supply is 3.3V as in the schematic.

You can also get 32-bit and 16-bit buffers, but 32-bit buffers are only available in 96-pin BGA housing and will be impossible to hand-solder.

74xxx16244 16-bit buffers are also available in 48-pinTSOP- and TSSOP-housing and can be hand-soldered.
You can get special 3.3 devices with 5V tolerant inputs, then you don't need to supply the 74xxx with 5V.

 

[se06745]

oscilloscope cpld

Hi!

You can use a 5v ->3v conversion driver like special 74xx244 with two VDD and GND. I used it, but now I don't remember IC part number.

Thanks!! 8)

 

[monnoliv]

dso-2150 schematic

Hi all,

I think your design need a DC compensation for the ADC input, as a DC adder to obtain the best ADC resolution range. It's necessary to put an adder configuration operational amplifier?

Where can I find an example ? Do you have a link? I didn't see compensation on bitscope for example. Thanks.

@monnoliv

You have switched pin 3 and 4 of all the HCPL-063L double optocouplers, U13, U14 and U15.
The LEDs will never turn on.

Thanks ME, it's corrected now in my schematics (upload soon, ).

For the protections, I added two SN74LVCH16244ADGGR on the 3V3 supply (then 3V3 and 5V tolerant inputs), upload soon.

ToDo: compensation/calibration unit + any other (cheap) idea.

After, I'll draw the PCB (or if another guy want to help...). I plan to use a four layers PCB for noise immunity. Any other Idea?

Regards,

 

[martingn]

oscilloscope fpga homemade

Hi all,

There is a good DSO input stage at http://www.johann-glaser.at/projects/DSO/analog/
He uses a DAC but it could be a pot with reference ( loosing the availability of self calibration because of bias drift )
He also uses MAX454x switch with a diode clamp for /10 input.

Do you all agree to start Input board using Eagle now? DXP is not available to download so it will be hard to find for most of us.

It will give us time to keep discusing with FPGA/board to use.
Input board will include the ADC.

Suggestions ????

best regards!

MArtin

 

[ME]

jyetech scope source code

Do you all agree to start Input board using Eagle now? DXP is not available to download so it will be hard to find for most of us.

I would rather use Protel DXP / 2004, it's still available at their website.
And it is also what he have already used to draw the schematics, so why change?
You can order a free trial CD-ROM with Protel 2004 evaluation version, the shipment is very fast.
Link to ordering page:
http://www.protel.com/evaluation/default.asp
http://www.protel.com/evaluation/request.asp

-----------------------------------------------------------------------------------

@monnoliv, two things:

1) I can't see any decoupling capacitors at all the VCC-GND pairs at the FPGA and at theExternal trigger op-amp, have you forgot to add them?

2) Don't you need a 5 kohm pull-up resistor at SDA on the 2-wire bus of U9 (ds1077z-100),
SDA is a two way line so you could get in trouble if the output of the FPGA is not an open collector pin.
SCL is only one way so I guess you can use totem-pole FPGA output for this.
A 5 kohm resistor is suggested at the top of page 8 in the datasheet:
**broken link removed**
Or have I missed something in the datasheet?

2-WIRE SERIAL DATA BUS
The DS1077 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls
the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must
be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1077 operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines, SDA and SCL. A pull-up resistor (5kohm) is
connected to SDA.

...
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
byte has been received. The master device must generate an extra clock pulse, which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. When the DS1077 EEPROM is being written to,
it will not be able to perform additional responses. In this case, the slave DS1077 will send a notacknowledge
to any data transfer request made by the master. It will resume normal operation when the
EEPROM operation is complete.
A master must signal an end-of-data to the slave by not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the
master to generate the STOP condition.

 

[monnoliv]

digital oscilloscope front end

Hi all,

Offset calibration done (trimmers) -> **broken link removed** (site is down now, wait until tomorrow morning GMT).

1) I can't see any decoupling capacitors at all the VCC-GND pairs at the FPGA and at theExternal trigger op-amp, have you forgot to add them?

Indeed, I'll make an overall check for decoupling when the schematics will be stable, soon I hope.

2) Don't you need a 5 kohm pull-up resistor at SDA on the 2-wire bus of U9 (ds1077z-100),
SDA is a two way line so you could get in trouble if the output of the FPGA is not an open collector pin.
SCL is only one way so I guess you can use totem-pole FPGA output for this.

That's a mistake indeed. Thanks you very much to check so deeply the schematics. Now I've corrected this by adding a mosphet and two resistors. FPGA command the SDA with an output pin via MOSPHET, reading is performed by a FPGA input pin.

When the schematics are stable, I can put them here if somebody is interested (Protel DXP only).

Regards,

 

[se06745]

tlc5540

Hi!

Well, first of all you need a digital line protections for the logical analizer. I find the IC part that I used : 74LVC4245AD it is a bidirectional buffer like 74xx245 permits 3v <-> 5v conversion in any direction.
You can use an optos to protect these lines too. The problem is the band width.

You always divides input signal 1:10 or 1:100 ¿Why can't you get the 1:1 input signal?

MAX4547 accept more than +-5v analog input signal??? You can crash it!!
I think that you need to use a monolitic relay in order to accept high voltage input signals.

Best Regards!

 

[monnoliv]

pc oscilloscope usb project

Hi,

Well, first of all you need a digital line protections for the logical analizer. I find the IC part that I used : 74LVC4245AD it is a bidirectional buffer like 74xx245 permits 3v <-> 5v conversion in any direction.

I use the SN74LVCH16244ADGGR, why this device isn't good for you ?

You always divides input signal 1:10 or 1:100 ¿Why can't you get the 1:1 input signal?

As I write on the explanations, I don't use the 1/1 level for a question of protection against overvoltages (with 1/10 and 1/100 you always have an equivalent source with high Z that is applied to the switch).

MAX4547 accept more than +-5v analog input signal???

In this case, the ESD diodes of the chip will conduct, since you have a high Z source impedance, current is limited and chip not destroyed.

See you,

 

[se06745]

ads831 oscilloscope

:lol:

Wouww!! Yes it's true with SN74LVCH16244ADGGR you can protect your input lines. Sorry I Haven't seen it!!!

But I think that your maximum amplification of the signal are x2

First you reduce 1:10 (resistor divisor) , after that you amplifies x10 (operational amplify mode) , finally amplifies x2 with AD8131 before of the ADC.

If you have a 2mVpp signal and want to amplify x10 ??

Well, your DC compensation look's well!! 8)

Best Regards!

 

[pisoiu]

jyetech oscilloscope schematics

Many logic analysers have the posibility to choose the type of logic levels sensed at input, so maybe comparators with adjustable levels for Vihmin and Vilmax are required. For example you won't be able to see PECL levels with a TTL buffer at input. Of course, this is if you want this feature installed...

/pisoiu

 

[ME]

max1180 development

Many logic analysers have the posibility to choose the type of logic levels sensed at input, so maybe comparators with adjustable levels for Vihmin and Vilmax are required. For example you won't be able to see PECL levels with a TTL buffer at input. Of course, this is if you want this feature installed...

/pisoiu

That is true.
I posted this design earlier in this topic:

Check out this application note from Xilinx too, this is probably the best way to design the input stage and protection:
https://www.xilinx.com/bvdocs/appnotes/xapp368.pdf
It's about how to design a Handheld Pocket Logic Analyzer.

Input Protection: Responsible for protecting the input comparator from excess voltage and
current. This protection scheme usually consists of a current-limiting resistor and a dual mode
transorb diode. This input protection circuit will have limits to its protection abilities. The user
should be careful not to apply an input voltage level that exceeds these limits. Input protection
was not implemented in this prototype.

The D-Flip Flops can just be implemented in the FPGA and the comparators
should be supplied from 5V.

Negative ECL 10k and 100k logic could also be detected if you use +-5V supply for the comparators and use special open collector comparators to avoid negative levels at the output.
Logic Levels standards: **broken link removed**
**broken link removed**

 

[pisoiu]

avr based oscilloscope

Yes, it is true, but I was thinking at a dual comparator scheme for each bit, one for low logic level maximum - Vilmax and one for high level voltage minimum - Vihmin. The treshold voltage for one comparator scheme would be set somewhere at the middle of uncertainty region, and this can show false results, especially in the case of heavy loaded busses. I think it is important to show a "0" or "1" logic level, exactely when the input gate see that signal in "0" or in "1", not in the moment when that signal passes the middle of uncertainty region. Heavy loaded busses have the tendency to slow the transition of the signal due to capacitive load, and this can cause sometimes violation of setup and hold times.

/pisoiu

 

[ME]

+oscilloscope +schematic

What should we do if a sample is made when the signal is in transition from low to high for example.
If the signal is in between the threshold area when the sample is made.
This is not because there is something wrong with the signal, but how should the software handle this situation?
The problem could be solved if we use an external clock from the D.U.T. circuit to trigger the samples as described in the Xilinx app. note as the 'State Analysis' method.
In the 'Timing Analysis' mode, there could be some samples made when the signal is in transition, maybe it should just be shown it as the last know value, or maybe it should show a third level in between ow and high?

In 'Timing Analysis' mode you don't know if the signal is in the undefined area because of a transition from low to high or because of too hevy load. Maybe the software should check if there was two samples in a row in the undefined area before it tells something is wrong.

In 'State Analysis' mode you won't have this problem, because you know when to sample correctly because of the external trigger timing.

 

[pisoiu]

oscilloscope schematic

What shuld we do if a sample is made when the signal is in transition from low to high for example.
I the signal is in between the threshold area when the sample is made.
This is not because there is something wrong with the signal, but how should the software handle this situation?
The problem could be solved if we use an external clock from the D.U.T. circuit to trigger the samples as described in the Xilinx app. note as the 'State Analysis' method.
IN the 'Timing Analysis' mode, there could be some samples made when the signal is in transition, maybe it should just be shown as low, or maybe it shoud show a third level in between ow and high?

First, we should not forget the analog point of view of this system. The Niquist criteria should be respected, and for this, the highest freq. component which we should consider is given by the formula F=1/2t, where t is the fastest transition (high to low or low to high) which we want to aquire. The max. freq. is not given by the signal freq. (ex. if this is a clock). So, the sampling freq. must be at least double than F. Also, I think the software should show when samples are in the uncertainty region, as well as it shows samples in "1" or "0" position. This will ensure a very accurate representation of the signal, and many erraticous-origin errors (due to pcb, noises, ground bouncing, poor decoupling, etc) should be easier pointed out. External clocks are an option for almost all logic analysers on the market, the only thing is that the processing path from DUT to acq. memory should have equal propagation delay with the processing path of the other signals.

/pisoiu