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Recent content by raviram80

  1. R

    Nofault blocks in ATPG for STA

    Hi All, I have a question regarding nofaults in ATPG tool, If I mark some block as no fault for ATPG vector generation, can I mark all the paths inside that block and from inside that block as false in STA runs?? ATPG tool will not put faults and generate patterns for such blocks Am I right...
  2. R

    Avoid optimizing particular RTL flop/logic in DC

    Hi All, I wanted to know how is it possible to avoid DC to optimizing a particular rtl flop so that DC does not remove it by optimizing since the flop has missing connection but is needed for further scan insertion Can you please tell me ? Thanks,
  3. R

    Hexadecimal to Binary for Odd Hexadecimal numbers

    Hi I have a simple question if there is an odd hexadecimal number 53'h70018_00001A1E What will be binary value ? how do you account for 53rd bit ? Please confirm Thanks,
  4. R

    Scanning DFT logic only in stuck-at but not in at-speed

    Hi All, I am using mentor fastscan, and there is some clock logic that can be scanned for stuck-at faults but not for at-speed. I wanted to know how is it possible to do that , like we can generate all the faults first for everything and then in at-speed only we can do something like add...
  5. R

    Technology affect on DFT Faults/Fault Models

    Hi All, I would like to know as the Technology decreases from 90 -> 65 -> 45 what are the possible faults that could be more prominent in lower technologies. Please let me know, Thanks
  6. R

    How to Handle Bidirection I/Os in ATPG Pattern Generation

    Hi All, I was reading an article about scan planning It said we should "Handle bidirectional I/O with care. Bidirectional I/Os can cause problems on testers, depending on how freely the ATPG tool chooses to operate them." What does that mean? How do we generally take care of BIdi I/Os...
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    DFT PLanning on a new chip

    JPV : you can mask the violating points by providing ignore list to the scan generation tool and it will be marked as X in the vector and so the response will not be compared.
  8. R

    Uncertainty defined on the ports

    Hi All, I would like to know what is the uncertainty in Primetime. Before CTS is done uncertainty is Clock Skew and Jitter. After CTS is done uncertainty is only Jitter. I would like to know what could be the uncertainty besides the Jitter. Please let me know. Thanks, Ravi
  9. R

    DFT PLanning on a new chip

    Also could I please know the answer to the second part of the question 2. The second scenario that I know of is when the Capture domain has two PLL at speed clocks which are high speed pulses generally output from On-chip clock generator. Now I know the below for the case above. 1. If I...
  10. R

    DFT PLanning on a new chip

    Hi Jpvsoccer, I could not understand your point as in how is this related to the question I asked, can you confirm if the capture we are talking about is not a slow speed capture and we are talking about Atspeed case as I ask in my question. Please let me know, Thanks,
  11. R

    set_clock_uncertainty in a design

    Hi All, After the CTS is done the clock skew is gone out of uncertainty. when we do set_clock_uncertainty in primetime what is left is Jitter number, Can you tell me what other things besides the Jitter could be contributing to Uncertainty? I am talking of both uncertainty for hold and setup...
  12. R

    DFT PLanning on a new chip

    Hi lostintxlation/jpvsoccer, I want to make sure here one thing here. I know two scenarios 1. Everything that you mention here about the capture pulse, Is that a high speed pulse.? Please Confirm this. I always used to think that we have a low speed capture pulse. in the designs that I...
  13. R

    DFT PLanning on a new chip

    Hi Jpvsoccer, You wrote this 5. How about clock domains? How to decide which flops of which domains can be combined or have to be kept in separate chains If possible, do not mix clock domains for test;it is a nightmare... If necessary, you may insert retiming latches OR ensure the stitching...
  14. R

    Folded Bitline in Memories

    Hi All, What does Folded Bitline and Open Bitline in Memories mean? Also how do we test them using Mbist? Please let me know, Thanks.
  15. R

    Memory in scan testing

    Hi, If the tool has capability of using Ram in scan test what happens to RAM outputs, because they are X....so could you please elaborate how this is done. Thanks, Ravi
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