Memory in scan testing

[raviram80]

Hi All,

I know one way of using Memory in scan test is to bypass its outputs using some top level signal. This ensures that we can test memory bist engine flops as well.

I want to know is there any other way of treating Memory besides the above during scan testing?

Please let me know,

Thanks,

 

[RBB]

Some ATPG tools have the capability of actually using the memory during the scan pattern.

 

[raviram80]

Hi,

If the tool has capability of using Ram in scan test what happens to RAM outputs, because they are X....so could you please elaborate how this is done.

Thanks,

Ravi

 

[lostinxlation]

there are many ways to handle the ATPG with memory.

- bypass the memory.
- having Muxes after memory outputs and feed some value to the muxes while testing.
- Design the memory to output deterministic value when certain pin is asserted.
- Initialize the momory before running ATPG.

The first 3 can be achieved by the regualr ATPG tool, but I don't think ATPG tool alone can handle the 4th one. you need a logic to initialize the memory.

 

[jpvSoccer]

Hi,

RAMBIST is a way to handle testing RAMs inside chips.

Tools automate the process of adding the BIST wrapper around the RAM.

Each RAM configuration will produce a signature that is shifted out of the RAMBIST structure and compared to a known good value.

 

[gmajay123]

I guess you can use some wrapper logic around a memory or analog block for better coverage in scan

 

[rca]

adding mux around memory, is not really the solution, that create a long path, in functional mode, stop by the memory, in scan not any more, so adding at least one flop during scan, to avoid a long path.
but when you add this logic, you need to test it also in scan. Then you need to find the threshold where the added logic help to find more fault than the logic itself add.

Simplify the ram model, reduce the number of fault, during the std cell scan, and in general, the memories are cover by a software/hardware bist.