raviram80
Member level 3
Hi Guys,
I would like to know your inputs on DFT PLanning needed for a new design partiularly
1. What flops to make scannable and which flops to avoid scannable
2. How to decide the number of chains?
3. Do we keep separate scan i/os or mux them with functional i/os? What would be the criteria for that?
4. How do we make sure that each flop is getting clock and reset? Is a separate test clock used or it is the functional clock?
5. How about clock domains? How to decide which flops of which domains can be combined or have to be kept in separate chains
6. Does PLL Atspeed vector generation play a deciding role in choosing which flops can be combined in one chain?
I know lot of questions, but it would help me as well as many others if you all can provide your inputs.
Please feel free to add more questions if you want. That will also help.
Thanks a lot,
I would like to know your inputs on DFT PLanning needed for a new design partiularly
1. What flops to make scannable and which flops to avoid scannable
2. How to decide the number of chains?
3. Do we keep separate scan i/os or mux them with functional i/os? What would be the criteria for that?
4. How do we make sure that each flop is getting clock and reset? Is a separate test clock used or it is the functional clock?
5. How about clock domains? How to decide which flops of which domains can be combined or have to be kept in separate chains
6. Does PLL Atspeed vector generation play a deciding role in choosing which flops can be combined in one chain?
I know lot of questions, but it would help me as well as many others if you all can provide your inputs.
Please feel free to add more questions if you want. That will also help.
Thanks a lot,