Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

set_clock_uncertainty in a design

Status
Not open for further replies.

raviram80

Member level 3
Member level 3
Joined
Jun 8, 2009
Messages
65
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,750
Hi All,

After the CTS is done the clock skew is gone out of uncertainty. when we do set_clock_uncertainty in primetime what is left is Jitter number,

Can you tell me what other things besides the Jitter could be contributing to Uncertainty?

I am talking of both uncertainty for hold and setup calculations.

Thanks a lot.
 

Hi, there is always clock skew after CTS.

CTS builds a clock tree that will have (hopefully) minimal skew or uncertainty, hopefully it has skew lower than what you told the synthesis tool, otherwise you will probably get timing violations

When you do STA and set clocks as propagated, the tool figures out all of the different arrival times from the source of the clock to the destination CK flop pins. the tools uses these arrival times to check for setup/hold slacks.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top