Scanning DFT logic only in stuck-at but not in at-speed

[raviram80]

Hi All,

I am using mentor fastscan, and there is some clock logic that can be scanned for stuck-at faults but not for at-speed. I wanted to know how is it possible to do that , like we can generate all the faults first for everything and then in at-speed only we can do something like add nofault


So basically make separate fault tables for both tests?

Please let me know since this is urgent

Thanks,

Ravi

 

[haykp]

e at-speed test is the same dft test, just the dft test run on the functional frequency of the circuit. So first you need to understand whether you can run at-speed dft test on your clock logic, whether your circuit support at-speed testing. If so, then there is no any special need to create a separate scan-chain for at-speed test.

 

[dbshailesh]

Ravi,
In your case you have to have a separate configuration saying you are in stuck at mode or in transition(TFT) mode,
So in tft mode the chain lengths will be lesser because you have to bypass the clock logic. By this way you can get the stuck at coverage on 'clock logic' but you can have the control over the 'clock logic' in tft mode.
For configuration either you can data_reg (P1500) or a top level pin which selects the stuck_at or TFT mode.

Is is clear now?
Regards,
Shail

 

[ConradATPG]

You are going to need a fast double clock pulse in order to do at-speed testing. You can do this from a pin, but it is better to use an on-chip PLL to provide your double clock pulses. Speed and precision is important and an on-chip PLL will be better in both these respects.