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pwq1999

Recent content by pwq1999

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relationally placed macros(rpm) problem

i creat rpm according to the software guide: 1. During synthesis,I/O insertion and the Creation of I/O Pads from Ports are disabled. 2.run floorplanner 3,After all of the components placed ,select File -> Write RPM to UCF.(i create ucf file and ngc file) but when i instantiate the rpm, the...
- pwq1999
- Thread
- Dec 26, 2008
- Replies: 0
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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I/O Buffer (IOB) vs. Global Clock I/O Buffer (GCLKIOB)

gclkiob xilinx just take a look at the language template, there are lots of example available.CLOCK_DEDICATED_ROUTE means that path is dedicated for clock,the path with least skew and is suitable to route clock.
- pwq1999
- Post #4
- Nov 3, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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ModelSim Problem: Licensing error

licensing error: the system date appears set back change your system date,it also works ok, i have met this problem, and your can search my post in this forum.
- pwq1999
- Post #7
- Sep 20, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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offset out constrain using the clock from dcm(xilinx)

ucf offset of dcm i use the dcm output signal CLKDV as my clock, and now i want to set the offset out constraint related to the clkdv, but when i write my ucf file, it reports error, so anyone can help me out ? thanks in advance!
- pwq1999
- Thread
- Aug 15, 2008
- Replies: 0
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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How to do the area constraint using floorplanner?

i want to use floorplanner to constrain my design by using area group constraint, and i want to follow the signal flow to assign my module in different place, now the problem i am encounting is that i found the right edge of floor planner didn't have pin number(pin location information). i think...
- pwq1999
- Thread
- Aug 12, 2008
- Replies: 0
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Driving a Bidrectional Signal in Verilog Testbench

you can use the "trireg",and maybe the link below can help you!
- pwq1999
- Post #3
- Aug 8, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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verilog code test with Spartan 3 AN

i2c master code verilog maybe you could use an external device as a I2c master,and communicate with the fpga(your I2c Slave). Chipscope is a good tool when using xilinx fpga.
- pwq1999
- Post #4
- Jul 31, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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signal names problem when viewing waveform in Chipscope

chipscope signal names when i use the chipscope generator, i connect the signals i want to view to the ila core, but when i view the signal waveform in chipScope, the signal names are ch0,ch1,~~~~ ,something like that in default, is there some way to change the signal name quick ? i don't want...
- pwq1999
- Thread
- Jul 31, 2008
- Replies: 0
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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synchronous reset (verilog)

thanks you all, i have change the synchronous reset to asynchronous reset, and no logic appear in front of the reset of the flip-flop,but i believe that kib's code works well, and thanks you all again!
- pwq1999
- Post #11
- Jul 27, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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synchronous reset (verilog)

i can not see your code have difference with the code i posted above!
- pwq1999
- Post #8
- Jul 25, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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synchronous reset (verilog)

thanks ,j_andr and research_vlsi, you two help me out! now i get the idea!
- pwq1999
- Post #6
- Jul 24, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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synchronous reset (verilog)

i want a multiplexer appear in front of the flip-flop, and the rtl8305_mtxen behaves as the select control signal. actually i don't want any logic appear in the reset input of the flip-flop, as i worry that it may make glitch in the reset input of flip-flop.
- pwq1999
- Post #3
- Jul 23, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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synchronous reset (verilog)

verilog counter with synchronous reset i write synchronous reset as follow: always@(posedge sys_clk_25m) begin if(!syn_rst_n) toggle_bit<=1'b0; else begin if(!rtl8305_mtxen) toggle_bit<=1'b0; else toggle_bit<=~toggle_bit; end end but when i view the RTL Schematic, i...
- pwq1999
- Thread
- Jul 23, 2008
- Replies: 10
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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How to start learning FPGA, what tools to use?

plz help dear pini_1, i can't open your website:**broken link removed** i don't know why i can't open it, i am in Shenzhen,China. sometimes i see you leave the website, but i never can open it.
- pwq1999
- Post #3
- Jul 19, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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simulation tricks using modelsim

yes, i am doing behavioral simulation of synchronous logic,but why some signal change with the clock concurrently, the clock sometimes can detect the right value and sometimes it doesn't ? thanks!
- pwq1999
- Post #3
- Jul 10, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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pwq1999

Welcome to EDAboard.com

Recent content by pwq1999

relationally placed macros(rpm) problem

I/O Buffer (IOB) vs. Global Clock I/O Buffer (GCLKIOB)

ModelSim Problem: Licensing error

offset out constrain using the clock from dcm(xilinx)

How to do the area constraint using floorplanner?

Driving a Bidrectional Signal in Verilog Testbench

verilog code test with Spartan 3 AN

signal names problem when viewing waveform in Chipscope

synchronous reset (verilog)

synchronous reset (verilog)

synchronous reset (verilog)

synchronous reset (verilog)

synchronous reset (verilog)

How to start learning FPGA, what tools to use?

simulation tricks using modelsim

Part and Inventory Search

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