Driving a Bidrectional Signal in Verilog Testbench

[Renjith]

Hi,
How to write the verilog testbench to drive a value to a bidirectional port.
Can someone suggest a simple example.

assuming a module has a bidirectional bus, clk,enable, RW

Thanks in advance

Renjith

 

[FvM]

I'm not using Verilog for testbenches, so I can't give an example. (I assume, Verilog textbooks do). But it's rather simple, you can drive either 0,1 or Z to each bit of the bus, as in a hardware test.

 

[pwq1999]

you can use the "trireg",and maybe the link below can help you!