pwq1999
Member level 2
verilog counter with synchronous reset
i write synchronous reset as follow:
always@(posedge sys_clk_25m)
begin
if(!syn_rst_n)
toggle_bit<=1'b0;
else
begin
if(!rtl8305_mtxen)
toggle_bit<=1'b0;
else
toggle_bit<=~toggle_bit;
end
end
but when i view the RTL Schematic, i found that the syn_rst_n signal make the logic or with the !rtl8305_mtxen signal ,which i don't expecte, so anyone can help me out how to express the synchronous reset without adding additional logic in reset input?
thanks in advance!
i write synchronous reset as follow:
always@(posedge sys_clk_25m)
begin
if(!syn_rst_n)
toggle_bit<=1'b0;
else
begin
if(!rtl8305_mtxen)
toggle_bit<=1'b0;
else
toggle_bit<=~toggle_bit;
end
end
but when i view the RTL Schematic, i found that the syn_rst_n signal make the logic or with the !rtl8305_mtxen signal ,which i don't expecte, so anyone can help me out how to express the synchronous reset without adding additional logic in reset input?
thanks in advance!