Still have problem with understanding `include in Verilog

[Xenon02]

Hello !

I'm still struggeling how does the `include works. I know there is something about name space although I don't really much understand it and also about duplicating the same wires and parameters. I know I could accept the fact that modules cannot be included in other modules but I couldn't understand it and I want to understand it fully because accepting the fact doesn't ease my curiosity and worry of not understanding it and stucking in a situation like : Should I use include or not or why it doesn't work when I included something.

Here is my example code of na ALU :

`include "alu_defines.vh"
module top_module(in_arg_A,in_arg_B,i_oper,in_clock,in_reset,out_result,in_carry,out_status);
parameter BITS = 10;
input logic signed [BITS-1:0] in_arg_A,in_arg_B;
input logic [1:0] i_oper;
input in_clock,in_reset;
output logic signed [BITS-1:0] out_result;
output logic [3:0] out_status;
input logic in_carry;
logic [BITS-1:0] out_mux;
logic [BITS-1:0] out_result_1;
logic [BITS-1:0] out_result_2;
logic [BITS-1:0] out_result_3;
logic [BITS-1:0] out_result_4;
logic [3:0] out_status_mux;
logic [3:0] out_status_1;
logic [3:0] out_status_2;
logic [3:0] out_status_3;
logic [3:0] out_status_4;
comparation #(.BITS(BITS)) Komparator (.in_arg_A(in_arg_A), .in_arg_B(in_arg_B), .out_result(out_result_1), .out_status(out_status_1));
right_shifter #(.BITS(BITS)) Shift (.in_arg_A(in_arg_A), .in_arg_B(in_arg_B), .out_result(out_result_2), .out_status(out_status_2));
subtractor #(.BITS(BITS)) Sub (.in_arg_A(in_arg_A),.in_arg_B(in_arg_B), .out_result(out_result_3), .out_status(out_status_3), .in_carry(in_carry));
//co należy podłączyć do wejścia out_carry
U2_changing #(.BITS(BITS)) Change (.in_arg_A(in_arg_A), .out_result(out_result_4), .out_status(out_status_4));
always@*
begin
{out_mux,out_status} = '0;
case(i_oper)
`ALU_COMPARATION: out_mux = out_result_1;
`ALU_RIGHT_SHIFFTER: out_mux = out_result_2;
`ALU_SUBTRACTOR: out_mux = out_result_3;
`ULU_U2_TO_ZM: out_mux = out_result_4;
default: out_mux = '0;
endcase
case(i_oper)
`ALU_COMPARATION: out_status_mux = out_status_1;
`ALU_RIGHT_SHIFFTER: out_status_mux = out_status_2;
`ALU_SUBTRACTOR: out_status_mux = out_status_3;
`ULU_U2_TO_ZM: out_status_mux = out_status_4;
default: out_status_mux = '0;
endcase
end

always_ff @(posedge in_clock)
begin

if (in_reset == 1 )
begin
out_result <= out_mux;
out_status <= out_status_mux;
end
else
begin
out_result = '0;
out_status = '0;
end
end
endmodule

and the include file :

`ifndef ALU_DEFINES
`define ALU_DEFINES
`define OPER_BITS 2
def∈eALUCOMPARATIONdef∈eALUCOMPARATIONOPER_BITS'd0
def∈eALURIGHTSHIFFTERdef∈eALURIGHTSHIFFTEROPER_BITS'd1
def∈eALUSUBTRACTORdef∈eALUSUBTRACTOROPER_BITS'd2
def∈eULUU2TOZMdef∈eULUU2TOZMOPER_BITS'd3
`endif

So what if I add " 'include Komparator" which is a module visible also in alu as comparator#.......
And what will happen if I delete in ALU the line with "comparation #(.BITS(BITS)) Komparator (.in_arg_A(in_arg_A), .in_arg_B(in_arg_B), .out_result(out_result_1), .out_status(out_status_1)); " and leave the line " 'include Komparator" as it is.

Why I still cannot use include ?

My guess is that when the Komparator file is compiled it's output and input can be used anywhere without inclusion because it has been "constructed". Then if I want to use Komparator in ALU and it's inputs and outputs it doesn't know which Komparator it wants to use (if it's the one he included or the one in another .sv file). Something like that ? Because it isn't about the sv file but the content which is modules sv file can have any name but when the content of the file has duplicated module name it doesn't know which module should be used in the rest of the project when it used the same module name.

I guess something like that came to my mind. I thought that duplicating the same part of the code wouldn't make any difference.

It was confusing for me sometimes because I saw this post : https://electronics.stackexchange.c...ude-statement-error-in-verilog-testbench-code. His include files containd the modules which already made me confused.

I know that include removes the include line and replaces it with that the include file contained. But I somehow couldn't understand what was the problem that the modules just duplicated. It's like the number PI was duplicated in couple of modules. Or compiling the same module in both different modules that contained this one duplicated module how it can overwrite it or something ? The content is the same so it cannot be overwrited the module so what is the problem with duplication ? Like I wrote above ? Because now when I write this part I got again confused ;>

 

[FvM]

1. Including a module as in the stackexchange example is legal Verilog but completely contradicting the idea of `include. In the context of your question, module names are in the global name space and therefore including a module twice in a project raises an error.
2. Typically you are including constants or type definitions. Using it in multiple project sources doesn't cause problems.
3. SV has more powerful means to import objects than simple include statement, e.g. classes.
4. If I understand right, the ifndef xxx define xxx construct quoted above is specifically used to handle problems of nested include files. We find it frequently in C code, but not so often in Verilog.

 

[Xenon02]

1. Including a module as in the stackexchange example is legal Verilog but completely contradicting the idea of `include. In the context of your question, module names are in the global name space and therefore including a module twice in a project raises an error.
2. Typically you are including constants or type definitions. Using it in multiple project sources doesn't cause problems.
3. SV has more powerful means to import objects than simple include statement, e.g. classes.

So I understand from your #1 is that the example from stackechange the author shouldn't include the module in the different module ?

Why those the global name space makes problem here if I include things twice ? It's like saying that this module is the same twice, it wasn't modified or anything. Or to better visualize it is that there is a constant 5 that is global like a = 5 and it is global and it appeared somewhere else also as a = 5 so it repeated. Why is it a problem then when it is not modified but appeared twice or even more ?

 

[FvM]

I see that we have discussed all these stuff time ago https://www.edaboard.com/threads/how-does-include-work-in-verilog.404881/post-1744823
Strange enough that you are still sticking with inappropriate including of modules.

 

[Xenon02]

I see that we have discussed all these stuff time ago https://www.edaboard.com/threads/how-does-include-work-in-verilog.404881/post-1744823
Strange enough that you are still sticking with inappropriate including of modules.

Yes I did mention at the beggining that I could accept but it didn't give me a break understanding it but I had to take a small break because I had a lot of things to figure out. I wanted to send a comment as soon as I get some time but then the post was blocked for any more comments. Of course this question came up to me when I came back to writing new verilog codes and couldn't answer this question by myself. I couldn't understand why global namespace blocked this option like repeating the same module in another module. It is the same module without any changes but repeated. It's like I coppy the code and paste it in different part of the code.
Maybe it makes no sense what I say but I just don't get it.

I need some example of why it doesn't work or some ilustration ? I know I demand alot but this simple thing of include that it copy the code and paste it whenever I use include is something universal. So I thought that including a whole module would be also okey, and hence I don't get it why the global namespace is the problem. I understand that once compiled module can be used everywhere but why including the same module in 2 or more modules will be a problem it's like compiling the same module without any changes like a = 5, 3 times. Hmmmm I might look wierd right now.

 

[FvM]

As already explained in the previous discussion:
To use a module inside another module, you simply compile them together in a project, no need to include anything. The module is known to others due to global module namespace.

 

[Xenon02]

As already explained in the previous discussion:
To use a module inside another module, you simply compile them together in a project, no need to include anything. The module is known to others due to global module namespace.

Like I said before why global namespace blocks the possibility of compiling duplicate module ? Like I've said before let's say a = 5 and it repeated 4 more times that a = 5 so nothing changed it is still a = 5 and it is global. Why the module that doesn't have changed code cannot be included in a different module ? The code of that duplicated module hasn't changed its like saying still that a = 5.

What my point is that it doesn't make sense to me that even though the module is global the duplicated module with the same code inside cannot be compilied more than once because it is still the same code. I think I can understand why the duplicated module name with different code inside of duplicated module cannot be compiled, because the program doesn't know which module to compile (they have the same name but different code inside) is it module with a = 5 or duplicated module name but a = 4.

Am I right here about duplicated modules but with different codes inside them ? If so then still why duplicated modules with the same code cannot be compiled it's like saying 4 times that a = 5, even though the module is global why it cannot compile the same module with the same code inside of that module ?

If my question isn't clear I will try again just let me know !
Thank you for your time :>

 

[FvM]

why global namespace blocks the possibility of compiling duplicate module

Why do you want to know this? It's no useful way to write Verilog code.

why duplicated modules with the same code cannot be compiled

Maybe because the compiler doesn't spend any effort on allowing useless things, e.g. to check duplicated modules for identity.
Most simple way to implement module namespace:
- add found module names to the name space, remember the module location
- if module name is duplicated, raise an error

 

[Xenon02]

Why do you want to know this? It's no useful way to write Verilog code.

I have used include of Module in other Modules and it didn't pop out any error then my teacher said it is illegal to do it. So I was wondering whether the program cannot understand there is the same module twice like a = 5 and a= 5 again or what.

Because it worked for me somehow while using for example Not_module which simply change the input into negative output and Included it into ALU module and it worked. I thought it was logical that I copied the module into another module and compiled both ALU SV file and Not_module SV file and it worked. So it saw two the same modules.

That's why I wanted to understand why is it having problem understanding the same modules in two different modules. When I saw it worked somehow in my case. It was logical for me that the program sees the same module twice so there shouldn't be any problem with compiling it as the same module.

Maybe because the compiler doesn't spend any effort on allowing useless things, e.g. to check duplicated modules for identity.
Most simple way to implement module namespace:
- add found module names to the name space, remember the module location
- if module name is duplicated, raise an error

Oh so it is not 100% sure why duplicated modules with the same code inside cannot be compiled ?

I know I might think to much about it so maybe what I say might be stupid. Just my speculation and what I was able to do which was compiling while having the module included in different module