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Recent content by easyads

  1. E

    questions about extract layout with calibre

    Hi I use calibre 2007 to extract layout. The layout is under tsmc 0.18um process. But I found there is some problem. Assuming that there is a mimcap between A and B. After the extraction, the mimcap between A and B is extracted out. But also another pararistic capacitor whose value is about...
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    Do the corner of different devices in tsmc has some relationship

    Hi ,all The following question is about tsmc 0.13um RF process 1. Do the corner of core device and IO device has some relationship? For example, if nmos1v goes to "tt" corner, then nmos3v will also go to "tt" corner? Or the nmos1v and nmos3v's corner has no correlation? 2. Please describe...
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    About the supply voltage of an inverter in tsmc 65nm LP process

    Hi An inverter with minimum channel length(L=65nm) in tsmc 65nm LP process is designed. The recommended supply voltage of the inverter from tsmc is 1.2V. (1) If the inverter is used as a static inverter, could the supply voltage vdd be more than 2.5V? （2） IF the inverter is used as an clk...
  4. E

    about RF circuit voltage supply in wlan chip

    Hi We want to design 802.11b/g soc chip. Perhaps we will choose 65nm or 90nm tsmc process. The digital core voltage and IO voltage of 65nm or 90nm are 1.2V and 3.3V respectively. 65nm or 90nm also provide 1.8V mos transistors. We are not decided which voltage transistors adopted...
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    question about clock shielding in RF system

    what is clock shielding In our system, system PLL generate CLK_24M for module ADC in RX. CLK_24M passes through module system PLL, RFPLL, TX and RX in turn and at last arrives at ADC. We want to use groud to do shielding for clock signal CLK_24M. The question is which groud should we use to...
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    ABout DC offset in 802.11b/g direct conversion receiver

    Hi We are designing an 802.11b/g direct conversion receiver. The main problem in direct conversion receiver is dc offset . There are several methods to solve this dc offset proble. The first method is to use HPF(RC HPF or analog seveo loop to realize HPF function) in analog baseband...
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    urgent, need some papaers about peak detector

    peak detector ghz I am designing two types of peak detector 1. cmos RF peak detector(2.4GHz) 2. cmos analog peak detector(10MHz) I have no account for IEEE. Could you please give me some reference papers about RF and analog peak detector? My email address is easyads@163.com Thanks
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    Need paper: Phase/freq detector phase noise contribution...

    Urgent! need a paper Would you please be so kine to email me This paper? My email is easyads@163.com Phase/frequency detector phase noise contribution in PLL frequencysynthesiser Brennan, P.V.; Thompson, I. Electronics Letters Volume 37, Issue 15, 19 Jul 2001 Page(s):939 - 940 Digital Object...
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    PFD noise contribution in PLL

    Thanks for your reply. We know that if the on time Ton of Charge pump decreases, the noise of Charge pump will also decrease. So i think if Ton is very small(about 1ns), the noise of Charge pump will be very negligible. And I think the loop filter will contribute the majority in band noise of...
  10. E

    PFD noise contribution in PLL

    We know that PFD, Charge pump,LOOP filter all contribute in-band noise for an integer-N PLL. Which is the main noise sources to contribute in-band noise, PFD or charge pump,or other block?[/img]
  11. E

    CMOS PA problem with exceeding 1.1 VDD

    I will design an cmos PA. The PA adopts fully diffential cascode architecture. The power control is realized by changing the output transistors size. So the VGD of M5 perhaps will exceed 1.1VDD. Is this a problem ? Or we can take some method 1. increase the L of nmos. 2. make the drain of...
  12. E

    can pss simulation predict oscillation of circuits?

    pss simulation can give the accurate frequecny of circuits under oscilltion. But you must check oscillator mode and first give the approximate oscillation beat frequecny handly.
  13. E

    How to control PA output power linearly?

    DDavid, I can not open your website to see your schematic. could you please post your schematic again?
  14. E

    How to control PA output power linearly?

    pa output power I am design a blutooth PA with output power 4dBm. But the output power must be controled from -30dBm to 4dBm. 1. How can power control be realized? Someome says that using an voltage attenuator to attenuate the input rf signal is an good method. How can an attenuator be...
  15. E

    How to improve 1dB compression point ?

    1dB compression point You want to increase P1dB. You must increase the current and overdrive voltage.
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