[SOLVED] Zero Delay simulation in Modelsim or ActiveHDL ...

[Oveis.Gharan]

Dear all
Is there anyone how know how can i simulate my post-synthesis simulation with zero delay mode. All the standard cells in library were set as unit delay and i want to set the delay as zero without library modification. Is there any switch in Modelsim or ActiveHDL simulation to nutralize all the timing lables and simulate all the system with zero delay gates?

Thanks in advance.
Oveis

 

[yura717]

Active-HDL
Zero Delay (Batch mode, Implementation Options Dialog Box)
By default, all non-zero delays are written to the appropriate output delay file. If this option is checked, no delays will be calculated or written to the output file.

 

[ljxpjpjljx]

you can simulate your netlist without any delay mode, then you can use zero-delay!

 

[Oveis.Gharan]

Dear yurav and ljxpjpjljx

Thanks for your attentions.
I have found just now the solution.
With "+time_mode_zero" switch in alog or vlog compile command, the simulation could be done as zero delay.

Thanks all for comments.
Best regards.
Oveis.