module MY_DESIGN ( Cin1, Cin2, Cout, data1, data2, sel, clk, out1, out2, out3);
input [4:0] Cin1, Cin2, data1, data2;
input sel, clk;
output [4:0] Cout, out1, out2, out3;
reg [4:0] R1, R2, R3, R4, out1, out2, out3;
wire [4:0] arth_o;
ARITH U1_ARITH ( .a(data1), .b(data2), .sel(sel), .out1(arth_o) );
COMBO U_COMBO ( .Cin1(Cin1), .Cin2(Cin2), .sel(sel), .Cout(Cout) );
always @ (posedge clk)
begin
R1 <= arth_o;
R2 <= data1 & data2;
R3 <= data1 + data2;
R4 <= R2 + R3;
end
always @ (out2, R1, R3, R4)
begin
out1 <= R1 + R3;
out2 <= R3 & R4;
out3 <= out2 - R3;
end
endmodule