ASIC_intl
Banned
wire load models, synthesis
Hello
I want to do synthesys without a wireload model and want to do timing report (report_timing) without wire load model. Do any body has any idea to do the synthesys and report_timing without wire load model.
Thanking,
ASIC
Hello
I want to do synthesys without a wireload model and want to do timing report (report_timing) without wire load model. Do any body has any idea to do the synthesys and report_timing without wire load model.
Thanking,
ASIC