Hello
I want to do synthesys without a wireload model and want to do timing report (report_timing) without wire load model. Do any body has any idea to do the synthesys and report_timing without wire load model.
synthesis & timing analysis without wireload models ????
AFAIK, Then the only available solution is to use
"Physical compiler" ( from Synopsys).
This tool can perform synthesis and STA ( pre-lyt) without the WLMs, cos the tool estimates the wire/net delays by virtually placing the cells during the synthesis stage !
I want to do synthesis only ( not timing analysis) without wire load model . Is it possible to do synthesis only in design compiler without wire load model? If yes then let me know.
If the synthesis can be done then I will come to know the critical paths in the design by using the report_timing command of design compiler.
To do synthesis without WLM you need to create a WLM within your .lib with zero capacitance and zero resistance, or you can create it separately and load it as a .lib.
Hi
WLM does not contain only R and C. It also contains area, Slope,fanout_length. I can cfreate a WLM with R-C=0. But what should be the values I should put for area, Slope,fanout_length in that WLM.
Added after 5 hours 59 minutes:
Hi Lakshman
Suppose I want to create a zero wire load model in the library. My library is in binary format .db. So I am unable to modify the binary library including the zero WLM.
Even if your library is binary you can still create a separate WLM and load it. This is not completely correct syntax wise, but use something like the following:
I do not have license to read a .lib file while using dc. So even if I have zero WLM I cannot load it or read it in DC. What are the other alternatives to solve this?
for simply synthesizing and checking the timing reports, without any WLM use the clock uncertainity level to >20% so that whatever the delays & extra R C & other cancel out w r t WLM when there is >20% of uncertainity. Hope iam true.
hw is it possbile ????
at the pre-layout level, WLMs will be used in datapath and clock path correct ???
hw can delaying the clock be a solution for WLMs ???
Setting the clock uncertainty higher only makes timing more difficult to meet, it does not impact interconnect delays. Sound like you got your library from a vendor, they usually will provide a zero wireload model in the library for unit delay analysis. Check with your vendor.
I tried to compile the .lib library using the read_lib command. But the design compiler says that you do not have library license to execute read_lib command. Do u mean this library license by your lib_compile license?
If u wanted to mean somet other license or some othe procedure please let me know.
without using wire load models in our script file ... the synthesis tool will take default wire load and then calculate the estimated delays of the paths..
wire load model is must for synthesis..
if wrong plz correct