Why do we only consider cap-load for STA?

[angadir]

Hi Ebody!

Why do we consider only cap-load for STA?

Thanks!

 

[roadbuster]

Why Cap load?

What other loads do you feel are important to consider?

 

[rjainv]

Re: Why Cap load?

What other loads do you feel are important to consider?

resistive load ????

While cap load is more meaningful as the amount of time a driver takes for its output to reach the new logical value depends on time taken to charge the capacitor at its output, but due to resistance between the output of driver, and input of next cell, the effective load of the receiving cell might be less at the driver ( search for resistive shielding).

Also, if you don't consider resistance, there is not slew degradation from output of driver to input of receiver, which again is not true.

In early prelayout stages while using wireload models, we do tend to ignore resistive load, as we are just modelling the parasitics.

 

[angadir]

Re: Why Cap load?

Thanks rjainv