How the intial utilisation is decided at PD stage. Why can’t we go with lower utilisation like 20% 30% ? Is it tech node dependent?

[smdaazz]

How the intial utilisation is decided at PD stage. Why can’t we go with lower utilisation like 20% 30% ? Is it tech node dependent?

 

[ThisIsNotSam]

Why would you like to go that low? It is far from optimal at that point, the generated circuit is going to be more power hungry and slower than the same circuit placed at 50% utilization

 

[Qwerty112233]

"How the intial utilisation is decided at PD stage."
How about you synthesize things in your technology, then look at std cell area from synthesis report.
This can be used to assume 50-60% beginning util and that can give you the area as

BOX_area = 2 * SYNTH_std_cell_area ; # for 50 % util

 

[smdaazz]

Why would you like to go that low? It is far from optimal at that point, the generated circuit is going to be more power hungry and slower than the same circuit placed at 50% utilization

Can you elaborate more

 

[smdaazz]

"How the intial utilisation is decided at PD stage."
How about you synthesize things in your technology, then look at std cell area from synthesis report.
This can be used to assume 50-60% beginning util and that can give you the area as

BOX_area = 2 * SYNTH_std_cell_area ; # for 50 % util

You mean to say Synthesis area report we consider as intial utilisation?
In placement stage utilisation increases just 2-3% because of std cells

 

[Qwerty112233]

Synthesis area report is just cell area. Utilization is cell area/ core area

You pick core area, if you want to waste money you can aim for 10 % utilization for your project.

More realistic is 50 55 % to start, then account 5 % for scan mbist..2 3% for hold fixing.

 

[ThisIsNotSam]

Synthesis area report is just cell area. Utilization is cell area/ core area

You pick core area, if you want to waste money you can aim for 10 % utilization for your project.

More realistic is 50 55 % to start, then account 5 % for scan mbist..2 3% for hold fixing.

careful with rules of thumb. it changes form tech to tech and stack to stack. having been doing this for 2 decades, I can say I have seen one tech where we would start from 40% and move up. reaching 50% was hell. In another tech, the starting point was 70%. reaching 80% was doable.

 

[Qwerty112233]

But in any design you need to at least find the breaking point as your due diligence. Start wherever, but build up to find where you start seeing shorts increase, timing crap out, runtimes explode. All part of knowing the design, this should be true regardless of tech node.

 

[ThisIsNotSam]

when pin access is the limiting factor, the design barely matters.

 

[Qwerty112233]

Yes that is true, those limitations can take floorplan sizing out of your hands sometimes. Then you end up with what you end up with : )

 

[dick_freebird]

Low utilization means larger die size and fewer possibles per wafer
leading to higher base cost per die.

If die cost is not the significant component of product cost then
you might elect to trade that for synthesis "wall time". But doing
it up front as a setting, rather than (say) putting a couple of
test cases into the hopper, seems like cart before horse.