why do we need SystemC language?

[tybhsl]

I only know SystemC is a language that can be used to facilitate system verification. And I am told that it can be converted into HDL. Can SystemC do everything that Verilog/VHDL can do? Will it replace them completely? Thanks!

 

[JesseKing]

system c is both a HVL and HDL. it can support system discription and rtl discription, so in some sense, you can think it can do everything that verilog/vhdl can do.

but i don't think it will replace them, because
1. it can not support rtl discription as efficient as verilog/vhdl, i think.
2. some other hvl languages are competing with systemC now, such as system verilog, open vera, and e. which one will win is still a problem.

 

[feel_on_on]

it is more colse to C language than HDL!

 

[andromeda]

Initially, idea behind systemC was: 1 language for everything hardware, verification and software.
Today, it is clear that no company made synthesis tool with SystemC support.
Still , even without usage in hardware description, SystemC has big advantage over SystemVerilog in SW/HW co-design and co-verification, SW/HW partitioning.
Also, iteration between different arhitectures is much faster in SystemC then in any HDL.
Todays simulator (for example cadence nc-verilog plus nc_systemc) have support for systemc/HDL cosimulation. That means great simplification and speed up in block level verification environments (developing of full model in SystemC and replacement of only 1 module with HDL description).
For system arhitects, SoC integrators (especially if there are some embedded processors there, and in average there are few of thrm in each SoC today), verification engeneers, even for design engeneers who want to have proper executabile specification before any HDL coding, SystemC is the language of choise.
I still want to see synthesis tool with SystemC support - that means very smooth iterations between various C++/SystemC models only with no discontinuitet.

 

[omara007]

SystemC is supposed to do what VHDL/Verilog do .. Yet, the main problem is that it's not supported by synthesis tools .. Dunno y !! ..

The advantages of SystemC over normal HDLs are:

1- It can support System Level Description and RTL, both.
2- It is executable, which means u can use it to communicate between design teams (like between Software Team and Hardware Team) without being annoyed by those guys don't know how to interprete what others say .. and overcome the background flavor of the various engineers.
3- You can still use the same code written for the system description in RTL description with the use of the normal C++ features (like overloading, overriding, inheretance, etc.)
4- It supports both SW and HW simulation simultaneously without any need to partition ur design from the very begining.
5- You can use any C/C++ statement inside the code, and this makes it more likely to spread among engineers because most of the engineers know C/C++.
6- SystemC comes with some ready examples and packages that are extremely useful for design .. something like IPs.
7- It's completely for free and u can use it on GCC. This makes it cheaper than VHDL and Verilog cuz if u go for HDL u need a simulator .. and most of those simulators are not for free.

 

[lijian_18]

I think SystemC is a very good tool for system design. The advantage of it is just speed. If connected with HDL, its advantage no longer exists.

 

[galant]

Actually systemc mostly used for system level verification now although there are some eda tools that can synthesis systemc into hdl.

 

[omara007]

there are some eda tools that can synthesis systemc into hdl.

Would u please tell me what are the available EDA tools that convert/synthesize (translate) SystemC to any HDL like VHDL or Verilog ?

 

[nand_gates]

Synopsys supports SystemC synthesis!
Check book by J. Bhaskar "SystemC Primer" for more info.

 

[omara007]

I have the book .. and I use SystemC at work .. and I guess Synopsis is no more supporting SystemC synthesis .. there are couple of available tool that pretend to be able to synthesize SystemC, yet the maximum they have reached is the behavioral synthesis ..
I already use Synopsis System Studio that supports SystemC simulation .. but I find nothing like a SystemC Synthesis in there ..
If u have an updated piece of info about this issue, please don't hesistate to update me ..

 

[andromeda]

If you use Cadence nc_verilog + nc_systemc, there is almost no slow down when you do systemc-verilog cosimulation (actually depending on Verilog module compelxity, slow down exists, but only because Verilog implemenation is inherently slower then C++/SystemC implementation - I really beleive that there is no language to language overhead). Probably it is not really cosimulation, but both languages are compiled into same internal presentation (I didnt check in Cadence documentation what they say about this).
So for everybody who hate cosumulations because of speed (Specman users, PLI users) in nc-systemc + nc_verilog there is no problem with this, what is really GREAT advantage.

 

[zhangpengyu]

Systemverilog is better than systemc.
Systemverilog is better than systemc,and can replace verilog and systemc.

 

[omara007]

Systemverilog is better than systemc.
Systemverilog is better than systemc,and can replace verilog and systemc.

why is SystemVerilog is better than SystemC ? .. and if this is true, why most of the EDA companies are supporting SystemC more than SystemVerilog ?

 

[quake]

Systemverilog is better than systemc.
Systemverilog is better than systemc,and can replace verilog and systemc.

why is SystemVerilog is better than SystemC ? .. and if this is true, why most of the EDA companies are supporting SystemC more than SystemVerilog ?

is it the case? I donnt think so. Zhangpengyu is right. Systemverilog can replace verilog and systemc. Not that many companies are supporting SystemC, and if they are, they only support a small sub-set of it, and some major companies have
already retreat FROM their systemC product. SystemVerilog is new and so advanced that some key functionalities are not easy to support, but I think lots of
big companies are doing that to catch the market in the near future since it definitely will become the trend.

 

[omara007]

is it the case? I donnt think so. Zhangpengyu is right. Systemverilog can replace verilog and systemc.

Well .. u claim so .. I guess it depends on what u r doing now .. maybe u use SystemVerilog .. so , u r fan of it .. but in reality .. we need evidences ..

Not that many companies are supporting SystemC

I think u r wrong in this .. simply because the fact says that big companies do support SystemC now ..

and if they are, they only support a small sub-set of it

What do u mean by subset of it !!!!!!! .. this is not a professional expression ! please specify exactly what u want .. and don't make it vague ..

SystemVerilog is new and so advanced that some key functionalities are not easy to support, but I think lots of big companies are doing that to catch the market in the near future since it definitely will become the trend.

Well .. hopfully this can be the future .. not only a dream ( Defintly is very hard word to be used in Technology ) ..

 

[quake]

Hi, omara007. Thanks for point out those points that
I think I didn't express myself clearly. You said maybe I use SystemVerilog now, yes, it's true that i
am preparing for it, but i have used SystemC and can feel its strength, still i can find some defects about it, like, not too many guys use it for synthesis. And some other problems that all we engineers will face often. Those company truly support it, but how often these tools are used in reality? A subset is realy a professional expression!
I mean the subset of systemC syntax and all functionality. It is not that vague, is that right? I should not use 'definitely', but it is my belief, every
EDA vendor has it own belief, and they may be extremely counterpart, who knows the future, it is just a kind of understanding.
Thanks

 

[omara007]

Dear Quake
Can u briefly state the advantages and the disadvantages of SystemVerilog ?
Regards
Omara007

 

[the_penetrator]

ok guys...

i'll try to be neutral here.

SystemVerilog hasn't got that much support yet. There are more SystemC-based tools.

Obviously SystemVerilog will ripoff VHDL and SystemC, and some Verilog constructs. It will try to be a better typed language with bridges to verification and system-level simulation.

But there is no really mature commercial tool (or am i wrong) and i can't seem to find any open-source tool for SystemVerilog.

BTW SystemC DOES HAVE capable open-source and FREE tools.

the_penetrator©
PS: I am a VHDL/SystemC user. Dropped Verilog around 2000. Expecting to see what happens with SystemVerilog.

 

[funzero]

We need it as a fast prototype tool.
It has a good quality at high level modeling and verification.

 

[spauls]

I am using system c from past 1 year,
it is best for Micro Architecture validation