why do we need SystemC language?

[omara007]

I agree that SystemC is gaining more support from all big EDA companies .. like Mentor Graphics .. Synopsis .. and Cadence .. At least some simulator like ModelSim is supporting SystemC long ago , hearning nothing about supporting SystemVerilog ..
I know that this doesn't mandate that SystemVerilog is worse than SystemC .. but SystemC is indeed gaining more importance .. and those big names care only about money .. so, I don't think ther are not selling their products ..
I still want to know more about the advantages and the disadvantages of the SystemVerilog ..

Regards

 

[the_penetrator]

omara007:

have you read the Lang. ref. namual from h**p://www.accellera.org. SystemVerilog looks nice but not better than SystemC. With SystemC we can potentially reuse the large C code base of simulators etc. that's already there. I have personally rewritten 2 simulators from C to SystemC past year.

That's about (plus some papers around conferences of cource) the only credible info. for SystemVerilog.

Around 2001, some guy stated: "VHDL the new Latin", shouting off VHDL as a *dead* language. It is easy to deduce that he was Verilog/SystemVerilog supporter doing his filthy job...

the_penetrator©

 

[omara007]

the_penetrator

I agree with what u said .. i believe that most of the people do judge other languages just because they are involved with some other ones ..
I myself am a VHDL/SystemC guy .. but am trying to be neutral .. yet, it's indeed true to say that SystemC seems leading SystemVerilog now in the market .. at least u can add it to any famouse C compiler .. it's all about some libraries ..

One good thing deserves mentioning that no one yet gave me any reply for my question .. What are the advantages and dis advantages of SystemVerilog .. seems no one is deeply involved with it even its fans

 

[wangxu]

In my opiniun, C and Verilog are enough for system and logic design .
there is no use in introducing Systemc language .

 

[omara007]

well .. SystemC helps u to do something like CLOCK, which u can't effectively introduce it in normal C .. can u ?

 

[zhaoyimiao]

SystemC is easy for architecture design and compared with VHDL/Verilog, it is easy to build behavior level model

 

[omara007]

I'll consider SystemC a real perfect language for all applications and can take over all HDL's , just if they can build a synthesis tool for it

 

[helios]

hi

systemC is an open source design and verification language bassed on c++. It allows engineers to apply powerful,proven software techiniques,such as OOD as in UML with the powerof C to solve the problems in system modeling and verification.Although applicable to system and hardware design . systemC is most effective as an verification language .


bye

 

[the_penetrator]

agree with most of you guys

anyway if it is going to be another breakout around this topic it is most likely to be:

1. UML and UML-> lower-level language translations.
2. integration of SystemC, UML, VHDL, cosimulations (have an IEEE standard for it)

If anyone has a pointer to freeware SystemVerilog tools, please post a message. I would like to have a quick hands-on SystemVerilog. Just curious. But I can;t decide if it is good or not that good, by reading some papers!

the_penetrator

 

[omara007]

One good thing about SystemC is that J. Bhaskar released ( SystemC Primer ) as he did with VHDL and Verilog .. Yet, I didn't hear about SystemVerilog's Primer from Bhaskar

 

[sarath51]

sysyemC is proving effiecinet for both Architectural modelling and verification

 

[jjww110]

systemc used for system level verification now although there are some eda tools that can synthesis systemc into hdl.it is inefficient

 

[power-twq]

It's more abstract, you can use it to do more complex things.

I only know SystemC is a language that can be used to facilitate system verification. And I am told that it can be converted into HDL. Can SystemC do everything that Verilog/VHDL can do? Will it replace them completely? Thanks!

 

[bianyh]

mentor c@t@pult could do the systemC -> RTL translation. I didn't tried it.