Do we need to check hold time violation between synchronizing flip-flops?

[ahmad898]

I have two-stage synchronizing strcuture consisting of two flip-flops. My question is that do we need to check hold time violation between flip-flops of synchronizer. Somewhere I read that these two flip-flops should be close together as much as possible and somewhere else I found that between these flops no combination logic is allowed as it may increase the metastability likelihood, but this may increase the hold violation as well.

 

[FvM]

Registers in the same clock domain are regularly covered by timing analysis, including hold time check. Are you considering to disable the timing check? Why?

 

[ahmad898]

Yes I want to aviod inserting buffer between synchronizer flip-flops as it reduces the MTBF.

 

[dpaul]

What you have read are both correct!
1. In some designs, to be really safe, you will observe that the engineer has put placement constraints on such sync flops such that tool places them as near as possible. But I also have designs running on hardware without such constraints.
2. You should not put any type of combi logic at such paths. Do whatever you have to do with the signal after the sync is done.
As FvM says above, the tool will by default do all type of timing analysis on the paths.

Have you already run timing analysis? Do you have hold problems?
If not just do it and see the results (do not get too carried away by what can happen or might happen)!

 

[ahmad898]

What you have read are both correct!
1. In some designs, to be really safe, you will observe that the engineer has put placement constraints on such sync flops such that tool places them as near as possible. But I also have designs running on hardware without such constraints.
2. You should not put any type of combi logic at such paths. Do whatever you have to do with the signal after the sync is done.
As FvM says above, the tool will by default do all type of timing analysis on the paths.

Have you already run timing analysis? Do you have hold problems?
If not just do it and see the results (do not get too carried away by what can happen or might happen)!

Thanks for your reply. I have already run timing analysis and I get the hold violation for the sync flops. So, here is the bottleneck. If I dont constraint such paths the tool will probably put some buffers between them when running optimization in P&R. I can put constraint on these paths with set_min_delay. But, the hold optimization will be ignored by tool. So, here again, do we need to be worry about hold violation between sync flops?

 

[oratie]

You should fix hold (and setup) violations between two FFs (synchronizer). Yes, no combinational logic allowed (but you fix hold by delay insertion, not logic). Yes, they should be close together as much as possible, but no hold violations.
If hold vios exist - the second FF may fall in metastability stage.