Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If you input signal is asynchron and being 1% of a cycle in a transition phase. Than there is a small analog voltage region at which it take longer to resolve into a valid analog voltage. The time to resolve a small voltage depend on the technology time constant. A rough estimate is Vcritical=Vlogic*exp(-Tresolve/Ttech). So a 0.13um running at 2GHz with 1.5V and 30ps make a critical region of 86.7nV. At these 500ps clock cycle with 30ps transistion the probability is for each cycle (86.7nV/1.5V)*(30ps/500ps)=3.47E-9. So with 2GHz each 1/(3.47E-9*2GHz)=144ms the DFF has to resolve a critical transistion signal and it take a full clock period. If you have a logic direct behind the DFF the time to resolve is smaller by your logic budget. If you cascade DFFs you increase the resolve time without reducing the sample rate.
The Master-Slave flip-flop construct by 2 latchs ,
The latch construct by 2 inverts connect back to back .
Draw the invert's transfer fuction Vout/Vin, the curve smoothly transit from high to low .
Now Add one another invert's transfer function , but change it from Vout/Vin to Vin/Vout . The 2 curve intercept in 3 points ,
(Vin=0 Vout=H) , (Vin=Vcc Vout=0) and 3rd point locate somewhere in the transition region of both invert's transfer function.
The 1st and 2nd points are stable , that means they can stay in these state forever . Once some noise push it offset from stable point , the direction is inward to stable point in 2 invert transfer curve . pull the offset back to its stable point . Conversly , the 3rd has the intendance to leave the intecept point and is astable . So if you have your signal setting the latch in either point 1 or 2 . It reach the stable points , but if you have your signal locate around in 3rd astable point . A small noise will change the direction from point1 to point2 or point2 to point1 . Even worse , it can jump back and forward in them . This is same situation as what make the invert to work for oscillaton .
Although it's the explanation for latch , the cause for metastable is same . You can run the spice with different conditions to confirm this .
but metastability is not the same as selfoscillating latches. There is already noise in the transition zone but this is not important for the synchronisation failures calculation.
Simulation of this event is very difficult. You have to adjust the starting ramp of the data relative to the clock. In increments of some femto seconds!!! Or using binary search and observe the data change. That simulation also give you the critical data window.
Also the definition of a failure is a little strict. So what happen if the DFF output stays for a hole clock period in the middle. It would be interpreted in the next logic gate either as zero or one. Otherwise the signal is not sensitive. So there is further down also a DFF. So a metastability failure does not mean circuit logic failure.
I agree with rfsystem in this one.
Let me try to rephrase a totally good explanation.
Each flip-flop is actually made of transistors.(Analog problem)
Therefore they have finite transition time. This means when they try to capture an input logic level there is a minimum voltage X which the FF decides it is '1' and there is another voltage Y which the FF decides the input is "0".
The question arises when the input is captured between X and Y. This range is the FF's metastability range.
Now coming to the next issue. Every architecture(geometry or process) has different speeds. The speed is how fast the output transitions when a logic level is changed. The slower it transitions, the more chances you have to catch the gate "pants down" or during this undefined region. When you catch a gate in this undefined region, where it ends up depends on so many things that you don't really want to know about!!!
The following appnote from Xilinx will tell you more about it.
Please look carefully to the diagram in the picture where the circuit claims to count metastability errors and analyze it. You may think that they are crazy because the steady state analysis says it cannot be different!
The difference in characters and transition are the input factor , the root cause is the astable mechanism built-in in circuits. That's why it call "metastable" . If the signal reach stable point (VH or VL) , the characters difference between flop still there . But it offset from astable state . So it keep statable state and unchange .
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.