metastability propagation in design

[ahmad898]

I have an annoying problem in one of my design, where the inputs are asynchronous related to the internal system clock. To solve the metastability propagation, I put two-stage flip-flop (two consecutive flip-flop connected to the input) to synchronize the input signals. However, when I simulate inputs with metastability (input changes at clock event) using Modelsim, I can clearly see that the metastability propagates from the first flip-flop to the second and the succeeding registers. My Question is that does this metastability exist at the output of the second flip-flop in the real world and do I need to be worried about the metastability at the inputs after inserting two-stage flip-flop?

 

[FvM]

What is the actual metastability MTBF achieved by your design? Metastability in a real system (unlike ModelSim) is a statistical problem. Adding registers doesn't "solve" its propagation, just makes it so unlikely that it won't happen in a reasonable interval, e.g. during system lifetime.

 

[ahmad898]

Thanks for your replay. I am not sure what is the value of MTBF for my design. But the operating frequency is 500 KHz and async data rate is very low (consider 50KHz worst case). The propagation time and setup time is about 26ps and 183ps for synchronizer, respectively. I use two-stage flip-flop at each async input. Also, another question, is there any guideline in placement or clock tree synthesis for synchronize flip-flop in physical stage?